Whatever the next step, experts on all sides say it will require an unprecedented collaboration between chip, board, connector and tool makers. Indeed some suggest beyond 10 Gbits engineers will have to carefully model the physical medium their signals will pass through before they can begin to define their signal technologies and the chips driving them.
"Customers are asking us to transmit 10G over various backplanes, some with less than tenth of the transmitted signal," said Eric Kvamme, a principal engineer developing serdes at LSI Corp., speaking on the DesignCon panel.
"You can't use the same methodology you used to for slower standards--sometimes standards need to define amounts of jitter specific to them, so we can generate and test signals in the face of a closed test eye," Kvamme said.
Serial links beyond 10 Gbits/s will require a return to analog methods such as continuous time equalization. But such analog techniques do not scale well when implemented in the latest process technology.
That could drive engineers to embed test instruments inside their silicon designs to more accurately measure bit error rates and other signals, said Mike Li, a principal serdes architect at Altera, also on the DesignCon panel.
Meanwhile the time it takes to test high speed chips is growing even as the ability of existing tools to cover all fault cases is shrinking, Li and others said. "You could have two billion word test patterns that don't even include a worst case scenario," said Ransom.
Pavel Zivny, a senior product engineer for sampling oscilloscopes at Tektronix called for a new quality metric to measure how well new tools actually work in the increasingly complex domain of high-speed signaling. Indeed, engineers expressed some anxiety they are entering a zone beyond the capabilities of today's tools.
An audience member at the DesignCon panel said all his tools failed to help him unravel problems with a high-speed system design loaded with crosstalk. "things were bouncing all over the place," he said.