By Tsu-Wei Ku, EEdesign
The fixed-die placement approach introduced more than 10 years ago was aimed at generating smaller dies
compared to the channel-based variable die techniques available at the time. The
improvements in terms of quality-of-results were so dramatic that virtually
every placement and routing system today uses this methodology.
In past technologies, the ratio between device size and minimum wire width
and spacing was large enough to reserve enough routing resources, so the
fixed-die approach yielded nearly 100% utilization. However, in today's deep
submicron technologies, shrinking device size no longer reserves enough wire
tracks to complete the routing. Hence, wire area has become a major factor in
completing a design. It is not uncommon that more than half of the modern chip
is occupied by "white space" or "inactive" areas.
The most common practice of exploring the solution-space of a design in terms
of optimal area with a fixed-die system is an ad-hoc trial-and-error method.
Designers usually start with a floorplan and take a guess at the amount of white
space needed for routing (utilization percentage). They then gradually shrink
the chip area until it becomes unroutable, or until timing can no longer be
But what complicates things is that timing, signal integrity and congestion
are all highly impacted by the quality of the placement results. Therefore, the
fixed-die approach, with its ad-hoc trial-and-error method, can no longer
predictably produce a chip with good area utilization that meets all other
design criteria. The fixed-die approach's inability to optimize its final
placement result for congestion, while maintaining timing, has become a
significant problem that can no longer be ignored in a modern physical design
The challenge of congestion relief
In current SoC designs for networking and communication-based circuits,
congestion is a dominant issue. Telecommunication switching circuits, cross bar
designs, and multimedia graphic chips all have numerous communication channels
with complicated multiplexing schemes. Such complex communication usually
creates routing congestion.
Common practices to resolve congestion are insertion of routing blockages so
that routing density is smaller around the congested zones, or enlargement of
chip or block size to have more routing resources in the congested areas. These
approaches may not always generate acceptable results because of the fact that
congestion depends on placement. Inserting routing blockages in the congested
areas changes placement and creates different congested areas.
Enlarging chip or block size will eventually produce a routable result, but
at a cost in terms of wasted extra space. Physical synthesis and clock tree
synthesis usually introduce additional congestion.
In some cases, a routable placement can become unroutable merely by adding
the clock tree. In these cases, designers often sacrifice quality by manually
inserting routing channels or by shrinking (or even removing) power rails to
gain more routing resources. If such manual modifications are not possible, the
only alternative is to enlarge the chip or block size again, re-run the design
and hope for the best.
A methodology for congestion relief
Not until recently has white space management appeared in any articles in
industry literature. This article proposes a mechanism to overcome the problems
mentioned above by using a predictable white space propagation technique. The
technique involves propagation of empty spaces to certain locations such that
congestion is alleviated and, if possible, die size is reduced.
During the white space propagation process, the timing behavior and the
relative location of cells are preserved. In order to first understand and then
manage the white space propagation process, the following information should be
used or generated:
I/O cell and bonding pad design rules
Each package has its own
bonding spacing rules. In most cases, bonding spacing rules at the corner of a
chip are different from regular spacing rules. It is important that I/O cells be
aligned with bonding pads in order to reduce the risk of electrical rule
violation or electro-migration.
Hard macro constraints
Many hard macro locations have their own
constraints. For example, analog modules such as PLLs (Phase Locked Loops) and
USB (Universal Serial Bus) interfaces must be tied closely to I/O cells to
reduce the chance of unwanted noise introduced by the digital portions of a
I/O pin constraints
As the size of a block changes, I/O pin
locations also have to be changed to meet the original position requirements of
Timing and routing constraints
Timing and routing constraints must
be examined continuously during the propagation process. Timing constraints
include setup and hold times, and clock-skew. Routing constraints include
routability, clock mesh, power mesh and rings.
Signal integrity constraints
Signal integrity issues are rather
difficult to handle during the propagation stage. However, global routing
information helps in estimating some of the major signal integrity issues, so
they can be handled by user-defined constraints such as avoiding long parallel
Usable space analysis
Not all of the empty space can be utilized
for propagation. It is important to understand how much space can be propagated
without affecting routing constraints.
With a great deal of effort expended to maintain the original relative
positions of the cells during the white space propagation process, signal
integrity and timing characteristics can be preserved. In certain cases where
the timing behavior is slightly distorted, the tool should have a physical
Examples of space propagation
A popular CPU core (Figure 1) was run through
an industry standard P&R system using timing-driven mode. Utilization was
set to 75%. The heaviest congestion was caused by a complicated communication
scheme in the TLB unit of the CPU. The resulting placement was un-routable, with
many highly congested hot spots (shown as red and yellow areas in the figure).
Usable space analysis found that 50% of the empty space could be propagated
to the congested areas. Figure 1 shows the before-and-after results of empty
space propagation. Note that almost all the congested red and yellow spots are
totally removed. The remaining congested global cells had overflows of 1 or 2.
An industry standard detail router was able to resolve these congested areas and
Figure 1a -- Before empty space propagation
Figure 1b -- After empty space propagation
Die size reduction
For the same design above, note that a further
reduction in module size is possible by propagating the empty space to the
right. The compaction tool automatically took congestion and timing into
consideration, and estimated that 10% of the standard cell space could be
propagated to the right. After space propagation, the original relative
positions of cells were maintained, as can be seen from module placement
highlighted using module coloring in Figure 2. In fact, timing (slack) improved
by 0.05ns after compaction. Although clock skew increased by 21ps, it was still
within the timing constraints for the design.
Figure 2a -- Before area reduction
Figure 2b -- After area reduction
With advanced white space propagation techniques, the empty space of a design
can be efficiently reduced while maintaining the design requirements that are
necessary to produce working silicon. Thus, unroutable designs can become
routable, and existing routable designs can be compacted.
Tsu-Wei Ku is the president and founder of Apex Design Systems Inc., a
startup company which promises to provide complimentary IC design solutions to
current design flows. Before founding Apex, he was the vice president of Arcadia
Design System, Inc. focusing on developing next generation datapath physical
solutions. He has multiple patents in the area of physical synthesis.