MANHASSET, NY -- Finding better ways thru semicondcutors and other devices to generate, transmit, use and save energy will be a large focus at the upcoming International Electron Devices Meeting.
The IEDM opens Monday, Dec. 6 with three plenary talks.
In his talk, Arunjai Mittal of Infineon Technologies AG will argue that the biggest potential for energy savings lies in the way we use our available energy, and that state-of-the-art power semiconductors and circuitry can help reduce losses along the entire electrical energy chain, from generation to distribution to consumption. He will describe a number of semiconductor technologies that can enable higher levels of energy-efficiency for lighting, electric motor drives, the power grid and other areas.
A symposium on power electronics technology will present 14 papers addressing crucial power and energy technologies.
An emerging technologies session of invited speakers will address next-generation power devices and technology. They include technologists from Texas Instruments, UC-Santa Barbara, TranSiC, ABB, Toyota and International Rectifier Corp.
In addition, eight papers will describe power semiconductors made from both silicon and non-silicon semiconducting materials from the following academic, industry and research institutions: Ohio State, Massachusetts Institute of Technology, IMEC, Hong Kong University of Science & Technology, Panasonic, North Carolina State University, University of Toronto, and Taiwan Semiconductor Manufacturing Co.
An evening panel session on Dec. 7 will debate: "Power Crunch -- Threat or Opportunity?"
The confluence of design and process technology and its ancillary power challenges will be addressed by a special session entitled: "Design challenges for non-conventional devices and 3-D LSIs".
Two papers stand out in that session.
An invited paper by researchers from Keio University will detail a ThruChip Interface (TCI) which uses inductive coupling for 3-D CMOS integration. It is implemented by digital circuits in a standard CMOS process and compares well with the more conventional thru-silicon via process in data rate (>10Gb/s/ch), reliability (BER<10-14), and energy dissipation (<0.1pJ/b), but is much less expensive. Its cost/performance is improved exponentially by thinning chip thickness.
A second invited paper from Embedded Systems Laboratory, EPFL, presents a novel thermal-aware design paradigm for 3-D ICs, developed in cooperation with IBM, that includes thermal modeling as a fundamental step to design 3-D multi-processor ICs with inter-tier liquid cooling microchannels. The modeling in combination with the use of dynamic thermal management at system-level to tune the flow rate of the coolant in each tier achieves thermally-balanced 3-D ICs, according to the researchers.
A groundbreaking paper more in line with IEDM's 56 years of presenting the latest crème de la crème of electron devices is an InGaAs Mosfet developed by a team led by University of Tokyo and including NIAIST and Sumitomo Chemical Co. The development is both the world’s first InGaAs Mosfet built on an insulating substrate, and also the thinnest InGaAs Mosfet ever made, with a tiny 3.5nm channel. Nonconducting substrates are key to the eventual integration of such devices with silicon CMOS architectures because they reduce short-channel effects, according to he researchers.
The team direct wafer-bonded the device to silicon and avoided creating unwanted source-drain junctions, which, because of the extremely thin films which make up the device, would have been difficult to anneal and would have made ion implantation difficult. Instead, they substituted an n-doped accumulation-mode channel.
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