When Samsung Electronics Co. Ltd. announced it would be the first to market with "30-nm-class" DDR3, the analysts at UBM TechInsights anxiously awaited a closer look at what was inside.Claiming to be the industry's first 30-nm-class SDRAM device, the Samsung K4B2G0846D has encouraged a healthy debate within our walls now that we have it on hand.
Primarily, most of the discussions have been on why and how the South Korean manufacturer can refer to their latest SDRAM offering with the term "30-nm-class."
Samsung K4B2G0846D 2Gbit DDR3 SDRAM
There are, of course, a number of different ways of measuring 'node' for SDRAM, so it's important to look at the big picture, and not focus too much on a specific measurement.
With that in mind, how does Samsung's newest stack up? To better understand the breadth of Samsung's newest SDRAM, here is a quick comparison of their DDR3 device to the recently analyzed DDR3 SDRAM devices from the other manufacturers at the previous process node:
Table 1: Comparison of DDR3 devices from different companies at different nodes
From the table, there are interesting findings that come to light when you take a look at the differences between the half-pitch metrics for each offering, and how that compares to the unit cell area. It is very interesting to note that where Samsung's Shallow Trench Isolation (STI) half-pitch is substantially smaller than its wordline half-pitch, the reverse is true for Micron Technology Inc.
Ultimately, manufacturers are looking for a reduction in cell area—and Samsung has now established a clear lead. So how did they do it? Looking at the above table, you can see that most of Samsung's shrink is in one dimension. Squeezing the STI by that much was quite the engineering feat.
To temper our enthusiasm, however, it must be noted though that it is a shrink in one dimension and the cell architecture has not changed; therefore it is still considered 6F2. This modified version of 6F2 architecture, however, still presents a reduction in cell area size of 38 percent on Samsung's 48-nm DRAM and a reduction in cell area size of 24 percent in comparison to Micron's 42-nm memory device.
Beyond the 'node'
Though our wordline half-pitch measurement indicates a process node of 46-nm, if we were to look at the half-pitch of the STI (a much tighter arrangement in this DRAM structure compared to previous generations), we could conceivably call this a 30-nm device. However, under traditional 6F2 architecture, if F was to equal 30-nm, the cell size should be 0.0054 um2 (the calculation comes from 2Fx 3F= (0.030um * 2) x (0.030 * 3)=0.0054um2), smaller than the cell size we have measured of 0.0085 um2.
For our measurement to match this area, the 'F' would indicate a process node between 37- and 38-nm. And therein lays the debate on how to classify this Samsung offering and why Samsung probably chose the naming convention of 30-nm-class. Regardless of how we want to define the 'node', we can all agree that this is a milestone in DRAM process technology for Samsung.
Cross-sectional image of Samsung 30-nm-class DRAM.
From a technology perspective, we're of course interested in far more than just cell size. Samsung has a history of introducing process changes well in advance of them being necessary. Kind of a test run to work out the inevitable kinks without the complications of trying to do everything at once. Has Samsung once again looked into the crystal ball, and worked to make the next generation that much easier to produce?
As the DRAM industry responds to this latest innovation, we'll be able to answer that question with more confidence.
We've also seen from Samsung's literature that there is a substantial improvement in low power characteristics. That may point to other process changes with this new generation beyond just the shrink. Some of these changes may prove to be just as interesting as the shrink itself, given the consumer implications in such a cut-throat market segment driven by cost and razor thin margins.
With this new device, the world's largest memory manufacturer aims to offer significant power savings to their customers while simultaneously lowering their own internal production costs. It remains to be seen, however, if this process shrink will translate to those goals.
Jason Abt is a senior product manager from the Technical Intelligence division of UBM TechInsights with over 14 years of experience in finding new approaches to analyzing the latest in semiconductor technology.
Dr. A. Dorofeevis a senior process analyst with 12 years of experience in analysis of silicon ICs and compound semiconductor devices for UBM TechInsights. He is very experienced in advanced process technologies and structures of flash memories, DRAMs, ASICs, processors and other devices.