As the world uses more and more mobile electronic products, controlling power consumption is the primary limiter of scaling semiconductor process technologies and adding features to integrated circuits. This power consumption is divided between active power (Pactive ~ CV2f), which is the power used while the product is performing its various functions, and leakage power (Pleakage ~ IV), which is the power consumed by unintended leakage that does not contribute to the IC’s function.
Leakage power has become a top concern for IC designers in deep submicron process technology nodes (65nm and below) because it has increased to 30-50% of the total IC power consumption. In addition, the leakage problem is worse than generally thought because the simple, traditional leakage power estimation of multiplying the average transistor leakage by the transistor width of the entire IC grossly underestimates the actual product leakage.
Leakage power is primarily the result of unwanted subthreshold current in the transistor channel when the transistor is turned off. This subthreshold-driven leakage power is strongly influenced by variations in the transistor threshold voltage VT (the voltage applied to the gate electrode that turns on the transistor). Transistor threshold voltage variation can be separated into two groups, global variation and local variation.
Global variation includes VT variation due to systematic process variations across a wafer or between different wafers. Examples include non-uniformities in doping, gate length, and film thicknesses (gate oxide, gate poly or metal, spacer, etc.). These systematic variations can be reduced by using a combination of optimized process flows, correction by applying adjusted bias conditions at sort, and device accounting through performance binning.
Local VT variations are not systematic but random, and some cannot be reduced by process optimization. The causes include random dopant fluctuations (RDFs) in the transistor channel, transistor gate line edge roughness, poly or metal gate granularity, and nanoscopic variations in gate oxide thickness. A primary contributor of local VT variations in deep submicron technologies is RDFs, which are generally considered to cause over 70% of local VT variations at the 65nm technology node, and these RDFs are becoming more significant as transistor channels become smaller.
Local VT variations occur across a very short distance and are quantified using VT measurements on sets of adjacent, matched transistors. This threshold voltage variation between adjacent transistors, called VT mismatch or sigma-VT (σVT), requires a statistical approach to product design to account for the random fluctuations of device characteristics.
To demonstrate the effects of σVT on total product leakage, consider Figure 1, which illustrates the VT distribution of two groups of 1,000,000 transistors with different values of local VT variation (σVT). While both VT distributions are symmetric Gaussian distributions, the set of transistors with larger σVT has a much wider distribution from higher to lower threshold voltages.
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Figure 2 shows the distribution of leakage power from the same two sets of transistors. The leakage power dissipated by a given transistor is given by P(Vt) = Vcc*Ioff (Vt), where Vcc is the applied voltage and Ioff is the leakage current for a transistor with this value of VT. The total leakage power dissipated by a group of transistors (such as a product) is therefore the product of the statistical distribution of VT and the leakage power function P(Vt).
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The total leakage power of each group of transistors is represented by the area under each curve in Figure 2. Note that the peak of the resulting leakage power distribution shifts from the center of the transistor VT distribution toward the lower VT values to the left. The shift indicates that the leakage power of a group of transistors is dominated by the transistors with lower threshold voltages because transistor leakage current increases exponentially as VT decreases. In this example the total leakage power of the set of transistors with σVT = 60mV is four times as large as the total leakage power of the set of transistors with σVT = 30mV.
Consequently, the simple leakage power estimation of multiplying the average transistor leakage by the transistor width of the entire IC product grossly underestimates the actual product leakage. In short, because Pleakage has an exponential dependency on transistor threshold voltage that is affected by σVT, IC designers should use the statistical approach described above to predict product-level leakage.
Beyond modeling the leakage power impact of local VT variation more accurately, the industry needs to change the trend of local VT variation getting worse with each new process technology generation and instead provide deep submicron process technologies with reduced local VT variation. Because random dopant fluctuations (RDFs) have become a fundamental cause of local VT variation, process and device engineers should innovate ways to address this significant problem. Transistors with undoped or lightly-doped channels, such as fully-depleted silicon-on-insulator (FD-SOI), are one method to reduce RDFs.
Lucian Shifren is director of device technology at SuVolta. Shifren earned BS, MS and PhD degrees in Electrical Engineering from Arizona State University and an MBA from Portland State University.