PORTLAND, Ore. -- On-chip busses and ring toplologies in use today will be more trouble than they
are worth, making on-chip mesh networks the preferred architecture for
massively parallel processors, according to according to researchers at the Massachusetts Institute of Technology (MIT).
"Future multi-core processors will have to communicate the same way
computers hooked to the Internet do--by bundling the information they
transmit into 'packets'. Each core will have its own router, which sends
a packet down any of several paths, depending on the condition of the
network as a whole, In short, rings scale better than buses,
but worse than meshes. Rings cannot scale much beyond 16," according to Li-Shiuan Peh, an associate
professor of electrical engineering and computer science at MIT.
An on-chip mesh network "lays a grid over all the cores, so there are many possible paths between nodes," said Peh. "Latency is much lower, with the disparity increasing as you scale up the core counts. Bandwidth is also much much higher because there are many possible paths to spread traffic across."
Intel used an on-chip mesh network with integrated router for its experimental 80-core TeraFLOPs processor of a few years ago, but the most sophisticated on-chip network on any production processor is the ring-network on its latest eight-core XeonE5-2600. Dropping back to a ring topology, however, is just a stop-gap, according to Peh, who claims his recent study shows that at 16-cores or above, Intel, IBM, ARM, Freescale, Samsung and every other multi-core processor maker will have to go to an on-chip mesh network with integrated router.
Today nearly all multi-core processors use a conventional bus architecture which overlays a bus above the cores to connect them to each other and to memory, but the last stop for the bus will be above quad-cores, according to Peh, prompting some chip makers to go to dual busses and Intel to go to a ring network topology for its Xeon E5-2600. Above 16-cores, however, all manufactures will have to adopt the Internet-on-a-chip topology.
Peh will present his results at the Design Automation Conference in June with fellow professor Anantha Chandrakasan and doctoral candidate Sunghyun Park. Their demonstration chip showed that 38 percent less energy is consumed by a packet-switched Internet-on-a-chip topology that uses voltage swings of just 300 millivolts.