The semiconductor industry is seeing increasing demand for miniaturization which necessitates changes in chip design, including larger numbers of I/O per unit space, multi-tier devices, and stacked dies that increase wire density.
Even the pitch - the horizontal distance between one wire and the next - is being reduced. This puts high demands on the stability of the wire bonding process, the bonding material properties, and their uniformity.
This article explores wire insulation and why it promises to be very effective in overcoming many of the challenges of meeting design rules for ever-decreasing chip sizes. Insulation would allow relaxation of design rules, not as a result of creating wire with better material properties, but rather because insulated wires would isolate one from the other, eliminating the need to avoid wires touching and creating short circuits. Relaxation of design rules would, thereby, simplify chip design and lower costs.
The article also provides information about the issues designers must consider when reducing wire diameter, including the “stiffness” during molding. Wires that are too small in diameter tend to have lower stiffness and change their position easily during molding. Requirements on molding compounds can be eased once the concern of short circuits is eliminated.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.