The semiconductor industry is seeing increasing demand for miniaturization which necessitates changes in chip design, including larger numbers of I/O per unit space, multi-tier devices, and stacked dies that increase wire density.
Even the pitch - the horizontal distance between one wire and the next - is being reduced. This puts high demands on the stability of the wire bonding process, the bonding material properties, and their uniformity.
This article explores wire insulation and why it promises to be very effective in overcoming many of the challenges of meeting design rules for ever-decreasing chip sizes. Insulation would allow relaxation of design rules, not as a result of creating wire with better material properties, but rather because insulated wires would isolate one from the other, eliminating the need to avoid wires touching and creating short circuits. Relaxation of design rules would, thereby, simplify chip design and lower costs.
The article also provides information about the issues designers must consider when reducing wire diameter, including the “stiffness” during molding. Wires that are too small in diameter tend to have lower stiffness and change their position easily during molding. Requirements on molding compounds can be eased once the concern of short circuits is eliminated.
Blog Doing Math in FPGAs Tom Burke 2 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...