Emerging wideband power line communication (PLC) networks are pushing transmit frequencies through 50 MHz today and soon through 100 MHz carriers.
In PLC networks, the line driver not only delivers the desired signal onto a difficult load but must also avoid introducing a non-linear load during its shutdown of this Time Division, Multiple Access system. One reason is that TDMA systems divide a single channel into a number of time slots.
Since these systems act like a party line on home power lines, where a single transmitter is enabled while all other PLC ports show a disabled line driver in parallel with the receivers, disabled ports must be able to receive signals without introducing excessive non-linearity into the broadband load.
Intersil engineers Raymond Ho and Michael Steffes discuss the test methodology for a 3rd-generation wideband differential driver.
In Part 1, they discuss the required characterization steps for a single port driver into a passive lab load.
Part 2 will focus on a second driver to the load network, showing a measurement setup for introducing active loads while tapping off the transmit signal for Multitone Power Ratio degradation measurement.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.