MANHASSET, N.Y. -- Memoir Systems Inc. is making its Renaissance 4X embedded memory IP technology available commercially and IBM MIcroelectronics is one of its first customers.
The technology is based on the company’s algorithmic memory IP technology that it claims offers a 4X increase in memory operations per second (MOPS) over competing embedded memory solutions.The solution eliminates the need to build custom multiport memories and can reduce area and power requirements by up to 60 percent compared to conventional physical multiport implementations, according to Memoir (Santa Clara, Calif.).
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Renaissance 4X can generate memories with any read/write combinations for up to four active ports, achieving 4,000 MOPS in a 28-nm process
"By working with Memoir, we can offer chip designers a highly efficient memory subsystem for SoCs that provides improved system throughput and fast time-to-market for complex products," said Robert Busch, a senior design engineer at IBM.
“All of the traditional multiport solutions have major shortcomings,” said Adam Kablanian, CEO of Memoir Systems. “Common amongst them are the high costs, risks and protracted development times that are associated with any custom silicon product."
Kablanian claimed Renaissance 4X is a "high performance, affordable, easy-to-use and versatile multiport memory solution that can address a wide range of requirements across the industry.”
Renaissance 4X meets the data requirements of next-generation SoCs used in networking and communication sub-systems which have aggregated speeds above 400 Gb/s. The Renaissance 4X can be applied for memories which require multiple memory accesses per cycle, such as packet buffers, counters, netflow, linked lists, schedulers, lookup tables, etc. In addition, Renaissance 4X provides multiport memories for shared L2 and L3 cache architectures, for high performance multicore SoCs.
Renaissance 4X Generators are available now and list pricing starts at $500,000 plus royalties.
Memoir Systems is based in Santa Clara and has development facilities in Hyderabad, India and Yerevan, Armenia. Related stories
From http://www.memoir-systems.com/index.php?option=com_content&view=article&id=73&Itemid=472 :
"by implementing a variety of techniques such as caching, virtualization, pipelining, and data encoding".
What exactly that means is not clear (and the whitepaper does not provide any significant additional information).
Address renaming (virtualization) could obviously be used manage bank conflicts. Bank conflicts could also be statistically reduced by _address_ encoding, but it is not clear that such would help worst case behavior even in the presence of other techniques. Pipelining could make temporal multiporting act as physical multiporting.
Their term Algorithmic Memory made me think that perhaps they exploited expected access patterns, but that appears not to be the case. The "algorithm" revers to the generation of a memory by algorithmic combination of standard components.
The major accomplishment here seems to be in making such transparent to the designer.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.