Core’s QZS plus GPS evaluation receiver measures 55 mm x 90 mm, runs at 5 V and is equipped with a USB interface to plug into a PC. The unit uses a board consisting of Texas Instruments’ OMAP-L138 MPU, a Xilinx FPGA and Rakon’s RF chip, GRM8652. It receives GPS L1-C/A signals the QZSS transmits. “When GPS signals get lost in urban canyons or mountainous regions, the L1-C/A signals will be especially effective,” explained Kurokawa.
Core claims its receiver is the first to process L1-SAIF signals transmitted by the QZSS. The L1-SAIF signals offer “ranging correction data” to improve positioning performance, said Kurakawa. “Our model has proven to provide submeter-class accuracy,” he claimed.
Core developed all key elements from scratch, including signal processing and control mechanisms. It also developed “patent-pending optimized algorithms” to measure global positioning and to recognize multipath, Kurokawa added.
Kurokawa said Core next hopes to develop a QZSS receiver that operates with GPS, GLONASS and other satellite navigation systems.
Core is also developing software-based QZS-plus GPS receiver designed to make it easier for developers to customize the QZS/GPS solutions. Kurokawa said only a few companies such as Sony Corp. are currently developing systems for the Japanese system.
The QZS plus GPS baseband receiver model is being made available to research organizations. The
evaluation unit is capable of producing observation files based on
L1-NEX format for research purposes.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.