PARIS – Achronix’s new 6 billion-transistor device, the first FPGA to be built on a 22-nm manufacturing process at Intel Corp. and promised to start sampling this quarter, won’t arrive in the market until the first quarter of 2013.
The HD 1000, the first in the Achronix family of FPGAs designated Speedster 22i HD, was supposed to reach the market before the end of this year.
Achronix Chairman John Lofton Holt (left) said the delay stemmed from “our design issues." He called the delay “disappointing.”
The Speedster22i HD family are SRAM-based, fully-reconfigurable FPGAs offering a familiar fabric architecture consisting of synchronous look-up tables, flops, muxes, carry chains, memories and multipliers, according to Achronix. Integrated with a variety of high-speed data communications interfaces, the Speedster22i FPGAs are designed to work in networking and telecommunications equipment.
Despite the delay, Holt said he remains confident about the HD 1000’s rollout early next year, insisting that the flagship FPGAs remain the company’s core business.
The delay, coming as Achronix is rolling out its strategy to enter the embedded FPGA IP business (disclosed several weeks prior to the product delay disclosure), could raise questions about where the eight-year-old FPGA company is headed. A fabless chip company entering the IP business is generally a long shot since the strategy requires an entirely new business model for a much tougher market.
IP licensing is an inherently long-term business. Before IP licensors can even think about royalties, licensees must first successfully design SoCs by using the licensed IP, then their chips must take off quickly when they hit the market.
Asked about it, the Achronix chairman laughed. “Yes, I know. The IP business tends to get people worried.”
Holt added that Achronix is not altering its business model. “Our core business still remains in high-performance, high-density FPGAs."
Good questions. At this point, Achronix is not naming names in terms of its potential customers or potential licensees.
But there appear to be demands for their physical chip. Who would be the first embedded FPGA IP licensee would be an interesting story to follow.
The IP strategy will be a tough, tough row to hoe... But remember, they're pretty much attached to Intel's hip and that's probably, long term, where the ip makes sense... especially as guys like Mark Bohr are saying the fabless model is dead.
how so resistion, perhaps i don't understand your meaning/reasoning there ?
lets say you have a given IP (Intellectual Property) for a generic SIMD engine with the same throughput as Neon, then as the node shrink's you can fit more interconnected engines together, and so less limited not more.
you may want to give better discount's per cluster of SIMD engine as it shrinks to make your version more popular than the competitors in the global markets rather than the old school fixed pricing etc.
Yes that's true by old school thought, but actually 28 nm and below, there are substantial material changes on all critical layers, plus litho constraints, you can't just work with any drawing you have.
The last succesful FPGA start-up company was Actel, who shipped their first product in 1988. You could say "it's been a while since then". Indeed, but not for lack of trying. More than 25 start-ups have tried and failed. Most failed by the nature of their FPGAs, and a few failed by the market barriers erected by the four FPGA vendors. You cannot make a business out of FPGAs by making a new FPGA that is slightly faster or slightly cheaper than what is out there. To succeed you must double the FPGA performance or cut the price-per-LUT by half. Acronix long ago claimed to have done the first of these, but they could not deliver on that promise, even with Intel's fanciest process. So they change the business model to survive for a little while longer. Everybody comments on how tough the IP business is, but the FPGA business is much tougher. Their new tack is an acknowledgement of this fact.
The devices announced by Archronix are designed for backend fabric, they are loaded with serdes. It seems odd that Holt is talking about mobile applications: power management is very weak in FPGAs, maybe they have a different kind of configurability in mind, to knit together some Intel IP.
I have not seen anything about design software yet from this company, which is normally a big concern for FPGAs. It makes me think Intel may have more of a hand in the overall enterprise here than is evident at this point.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.