While current customers can already use virtual machines with previous generations of the MIPS architecture, Gardner said the new MIPS virtualization module “just makes it easier for software companies to virtualize the CPU hardware.” It also allows “unmodified operating systems to run more efficiently on a Release 5-enabled Virtual Machine Manager,” he added. In essence, MIPS Release 5 is designed to “welcome guest operating systems.”
MIPS isn’t alone offering virtualization features. “ARM and x86 have fully embraced this technology in computing platforms that range from low-cost mobile processors to supercomputers. Even some of the smallest embedded systems are using virtualization to create an isolated environment for secure processing that runs on the same CPU with other operating systems,” explained Gardner.
With the virtualization module in MIPS Release 5, “these guest operating systems are more secure because they run in separate guest kernels instead of user space,” the analyst added. “This extra privilege level also keeps a guest operating system crash from bringing down the other guests.”
In addition to virtualization, Release 5 includes 150 new instructions for SIMD processing of 128-bit vectors. The MIPS SIMD architecture module is designed to allow efficient parallel processing of vector operations. “MIPS has been in the sweet spots of digital living room,” claimed Throndson. “SIMD offers support for heavy-duty multimedia applications, including HD encoding, decoding, communications, audio, image and graphics processing.”
Another problem between silicon implementation and next-product design is that new standards can emerge. When that happens, Throndson said the SIMD architecture allows vendors to run “good enough” software on the processor core.
Gardner said the new SIMD instructions will improve DSP performance. “This should allow the MIPS CPUs to save power on applications such as audio processing."
Gardner added that the MIPS SIMD Architecture (MSA) instructions are a major upgrade. “Instead of constraining the instructions to operate on data packed within the 64-bit floating-point register file, the MSA instructions are true vector operations not limited by a specific hardware implementation," he said.
Reviewing the MIPS Release 5, Jim McGregor, founder and pricipal analyst at TIRIAS Research, said, "The MIPS architecture has lagged in areas such as virtualization and SIMD, partially due to a focus on high-end and embedded applications that have not required these functions, and partially by a lower level (or lack of) development."
He described MIPS "kind of fell into a hole," because the company relied on incremental improvements and licenses for quite some time. "However, over the past two years, MIPS has come alive again, and will likely see more investment in R&D going forward when it is combined with either CEVA or Imagination," he added.
Gardner speculated that the next version of the MIPS architectural update “may be heavily influenced by the business focus of the new owners, perhaps adding new instructions to support heterogeneous processing with a MIPS-optimized graphics core.”
He added, “The Release 5 instructions should be easy to fold into the existing software development tools, and MIPS licensees can get started right away with the existing GCC [GNU Compiler Collection] tools.”
The Linley group expects that Broadcom will offer “one of the first announced products to use Release 5.” Broadcom is investing in getting the virtualization features supported by Xen and others, Gardner added.
MIPS hasn’t announced which of its own Aptiv family of cores will support R5 virtualization and MSA, but “MIPS designers undoubtedly have these designs underway and are just waiting for the dust to settle on the acquisition before committing to public release of new licensable cores,” Gardner said.
To sum up, the announcement by MIPS' engineering team came out almost in defiance to the company’s still uncertain fate, and in what looks like a celebration of the MIPS architecture’s stubborn survival over the last 30 years. The new technology announcement has garnered praise from customers, partners and legends in the industry, as though they are all saying, “Long live MIPS!”
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.