MANHASSET, NY -- In 3-D IC designs, multiple chips in a package are closely stacked up through connections of TSVs and micro-bumps. These versatile connections allow more functionality to be compressed into a small footprint for chips targeting low-power mobile, high-performance computing, and consumer and automotive electronics.
However, a key challenge with 3-D IC system environments is thermal interactions and thermal-induced stress failures because of the higher temperatures and complex thermal distribution. For instance, temperature profiles on a 3-D IC are the result of thermal interactions with other chips, thermal conductive paths in a package, the PCB the package is mounted on that has other heating components, multiple PCBs, airflows and radiations inside the box, and the thermal environment outside the box.
To solve the temperature challenges of 3-D IC or silicon interposer-based designs with TSVs requires using advanced modeling, simulation and debug capabilities that includes a detailed chip power map of the device and metal layers in order to achieve accurate thermal distribution and incorporating system thermal simulation in the power-thermal loop.
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In a paper by Norman Chang, who co-founded Apache Design Solutions, to be delivered on Tuesday, January 29 at DesignCon
will feature real case studies of temperature solutions for chips, thermal back-annotation for chip reliability and performance, system impact on chip temperatures, and transient responses of power mode changes in 3-D ICs using ANSYS-Apache technology.
The paper name is Thermal Co-analysis of 3-D IC/Packages/System
, and is part of session 4 at DesignCon, which runs January 28-31.
The methodology flow presented in the paper will demonstrate the link between the 3-D IC package thermal simulation with the system (PCB/box) thermal simulation through the exchange of power maps per die and thermal boundary conditions that will enable chip-package-system design sign-off on thermal/stress aspects and provide an accurate thermal chip solution.
Chang serves as VP and Sr. Product Strategist at Apache Design, Inc., a subsidiary of ANSYS. Prior to Apache, Chang led a group at Palo Alto HP Labs, focused on interconnect-related signal/power integrity issues and contributed to the HP-Intel IA64 micro-processor design. He received his B.S., M.S., and Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley and is co-author the popular book, "Interconnect Analysis and Synthesis.” Chang is currently on the committee for ESDA-EDA, and Chair of the Si2 Open3D PDN workgroup.
Apache's RTL Power Model was named in UBMTech’s EDN
Hot 100 Products of 2012. In 2004 EE Times
listed Apache on its Top 60 Emerging Semiconductor Companies Worldwide.