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TSMC starts FinFETs in 2013, tries EUV at 10 nm

4/11/2013 12:18 PM EDT
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resistion
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
resistion   6/2/2013 9:43:50 AM
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EUV source wall-plug power is 0.5 megawatt. Crazy. http://semimd.com/watts/2013/03/14/cymer’s-euv-team-has-an-exciting-few-months/

double-o-nothing
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
double-o-nothing   5/5/2013 2:12:07 AM
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"Even if EUV hits its targets, the 10nm node also requires use of self-aligning techniques with immersion lithography to minimize the need for EUV to just some critical layers. TSMC also is developing a so-called G-rule that automates the tricky process of handling color conflicts in double patterning." It would be implied that no EUV layers would be best otherwise why all the trouble with the double patterning.

resistion
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
resistion   5/4/2013 2:34:19 PM
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God also gave electrons mean free paths, so I doubt EUV or E-beam are the intended windows for lithography. http://www.google.com.tw/imgres?imgurl=http://www.virginia.edu/ep/SurfaceScience/mfp-luth.GIF&imgrefurl=http://www.virginia.edu/ep/SurfaceScience/diffract.html&h=1306&w=1760&sz=44&tbnid=QKsyadnm5B9OOM:&tbnh=92&tbnw=124&prev=/search%3Fq%3Delectron%2Bmean%2Bfree%2Bpath%26tbm%3Disch%26tbo%3Du&zoom=1&q=electron+mean+free+path&usg=__bB9cU--iCG-n29qsTr83sRrdjcg=&docid=jwiPBTm96sPScM&sa=X&ei=RRuFUdKrEM2jkQXxsYH4Cg&ved=0CDsQ9QEwAw&dur=156

resistion
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
resistion   5/4/2013 5:22:58 AM
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Optical is not ending, there's perseverance there as well.

Mickey.Taiwan
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Mickey.Taiwan   5/4/2013 4:12:19 AM
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God closes a door (optical lithography), he opens a widow for those who are with perseverance. It takes time and let's see.

Diogenes53
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Diogenes53   4/21/2013 4:27:15 PM
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Burn Lin should have retired as the Holy Father of Immersion, basically saving an industry which made another obviously foolish bet on X-ray lithography (oh, sorry: EUV lithography) and while saving us from a 157nm black hole. The trouble with such success is it can breed hubris. Lin's E-beam direct write has had a similar history to X-ray. The end of optical seems around the corner, billions are spent on alternatives, all fail; now, the end of optical seems even closer, so the failures are renamed (EUV and maskless), more resources are wasted, but Mother Nature doesn't pay attention to marketing-created name-changes. Refocusing from X-ray to EBDW means instead of the overwhelming challenges of source, resist, and mask/blank, we have the overwhelming challenges of source, resist, throughput, and data path.

NichiconLF
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
NichiconLF   4/21/2013 7:29:14 AM
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I am not sure... http://www.xbitlabs.com/news/mobile/display/20130320235000_Nvidia_Reveals_Kayla_Platform_for_Developers_of_GPU_Accelerated_ARM_Applications.html

rick merritt
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
rick merritt   4/17/2013 9:00:09 PM
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Have they announced that? What's your source?

the_floating_ gate
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
the_floating_ gate   4/16/2013 4:23:19 AM
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Who does direct write? ASML bought SVG and ASML killed it. Direct write goes back to Eaton? SUMMARY OF THE INVENTION An object of the present invention is to provide an improved electron beam lithography method for creating an exposure pattern having unprecedented resolution in an electron sensitive surface. This is accomplished in accordance with this invention by patternwise treating an electron sensitive surface to a high resolution pattern of low-energy electrons rather than high-energy electrons. ....... When the separation between the pointed electrode and the surface being treated is less than about 1 nm, the electron clouds of the atoms at the apex of the pointed electrode and at the surface opposite the apex touch, and a tunnel current path is established between the apex of the pointed electrode and the surface. When the separation is more than about 3 nm, electrons must leave the pointed source via field emission. When the separation is between about 1 and 3 nm, both current effects are experienced. In any case, the area of the surface receiving the electrons has a diameter roughly equal to the distance between the point source of the electrons and the target surface.

Dolphin7835
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Dolphin7835   4/15/2013 5:39:44 AM
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IEEE Computer Society of Santa Clara Valley has a 2 day symposium April 18-19, where the Friday is focussing on FinFET. http://www.eda.org/edps/

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