Some industry watchers say 20 nm will be an interim node to work out the wrinkles in double patterning lithography, but not offering many advantages to chip designers. Don’t tell that to Jack Sun, chief technology officer of TSMC.
By 2017 he predicts the Taiwan foundry will be making as many 20-nm chips as it 28-nm ones. He claims the node will offer a 1.9x increase in gate-level density over the high-performance 28-nm node, although some speculate rival Globalfoundries will only deliver a 16 percent density increase at 20 nm.
Sun also said 20-nm chips could sport 20 percent higher speeds or 30 percent less power consumption than 28-nm ones. That’s significant though not as much as traditional full nodes. The 16-nm node that follows it will have similar characteristics, but a future 10-nm node will have slightly greater benefits, he said.
TSMC expects to have about 20 tapeouts at the 20-nm node this year at its fab 12 and 14 plants. Mass production at that node really starts in 2014, said Wang.
The 20-nm node will be as big as the 28nm node by 2017, Sun predicts.
Designs using an 80 to 90-nm pitch can be designed using single patterning. But more fine lines will require a second pass under the immersion lithography scanner.
The ecosystem is ready, said Cliff Hou, vice president of R&D at TSMC. Some 38 features of 28 EDA tools have been tested for 20 nm, 185 design kits are available for the node and both foundation and critical interface IP blocks have been verified, he said.
TSMC expects silicon back in May on a 20-nm test device based on an ARM Cortex A15 core, Hou said.