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TSMC starts FinFETs in 2013, tries EUV at 10 nm

4/11/2013 12:18 PM EDT
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resistion
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
resistion   4/11/2013 7:27:16 PM
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Won't even have enough EUV tools by 2015 for 10 nm.

Diogenes53
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Diogenes53   4/14/2013 11:33:07 PM
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Is 0 not enough?

the_floating_ gate
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
the_floating_ gate   4/12/2013 2:39:48 AM
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bunch of hyping - some very recent quotes from ASML (UBS Technology conference) "we are starting this later this year" "This is really essential in terms, because if you have this machine on its own, it does overlay accuracy 5-nanometers to 6-nanometers. 5-nanometers to 6-nanometers is not good enough for double-patterning, you need to have something closer to 2-nanometers to have a double-patterning accuracy that allows yields to be acceptable and yields are related to prices wafer prices et cetera, et cetera. So in fact, this is the key, having this is the key to be able to do 20-nanometer processing in production at acceptable cost and we have one major customer who is engaging in this and we are starting this later this year. This was immersion, but immersion, water immersion and double-patterning immersion going to be with us for a long time, you could almost say forever.... The more you start to look into the details where an eagle is it looks like when you go to a 14-nanometer logic design, which they will call 10 or 11 or 9 in terms of nomenclature they also call 20-nanometer 16 and 14 and it’s one big mess in terms of how do you call it. But if you look at it in terms of lithography point of view, 14-nanometer lines which is the next generation. It comes after 20 is awfully, awfully difficult in double-patterning left below multiple-patterning and if at all you are able to do it, you are imposing yourself a lot of design restrictions, limitations and also at significant higher cost.

RobDinsmore
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
RobDinsmore   4/12/2013 4:19:05 PM
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This kind of explains TSMC's recent push. What I don't understand in all this is the 4 years they project for 450 immersion. Why will it take so long if there are customers that want to start running 450 wafers in 2015?

Jack.L
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Jack.L   4/12/2013 4:55:24 PM
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RobDinsmore, what customers want to start running and what may be technical/economically feasible are not always in line. I liked their 2017 wafer start projection "if we keep growing". Moore's law may apply to chip features, but I don't think it applies to companies ... though continuous unsupported growth has often been in business models... till they fail.

skyhawk2
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
skyhawk2   4/12/2013 9:11:22 PM
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The key question here is will Morris Change lasts until 2015. Interesting time ahead for TSMC.

the_floating_ gate
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
the_floating_ gate   4/13/2013 2:29:40 AM
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TSMC goal/objective for 2013 is to increase 28nm HKMG / 28 SiON to more than 50% , NVDA is delayed because they can't get 28nm HKMG wafers!!! TSMC FinFet = 20 nm design rules = muted die shrink this is the real world

NichiconLF
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
NichiconLF   4/13/2013 4:27:10 AM
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Nvidia will move to globalfoundries for 14nm xm

the_floating_ gate
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
the_floating_ gate   4/14/2013 5:47:29 AM
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Nvidia will move to globalfoundries for 14nm xm.... Good for NVDA.... I suppose Intel is not interested in NVDA business... there goes another major TSMC customer

rick merritt
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
rick merritt   4/17/2013 9:00:09 PM
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Have they announced that? What's your source?

NichiconLF
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
NichiconLF   4/21/2013 7:29:14 AM
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I am not sure... http://www.xbitlabs.com/news/mobile/display/20130320235000_Nvidia_Reveals_Kayla_Platform_for_Developers_of_GPU_Accelerated_ARM_Applications.html

blacklighting
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
blacklighting   4/14/2013 11:04:32 PM
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my manager just came back from a visit with all the foundries. His report called all the post 20nm work (finfet, EUV, 450mm ) as "power point". EUV being the best examples. .....still fundamental physic uncertainty but TSMC, GF have it on roadmap for 2015 production. most of our future designs will be targeted to the last moore's law node "28nn"

Diogenes53
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Diogenes53   4/14/2013 11:48:25 PM
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Let's see: EUV in 2015 at 10nm or ebeam direct write? Balanced budget or universal health care in 2015? Jacksonville Jaguars or Kansas City Chiefs in the 2015 Super Bowl?

Dolphin7835
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Dolphin7835   4/15/2013 5:39:44 AM
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IEEE Computer Society of Santa Clara Valley has a 2 day symposium April 18-19, where the Friday is focussing on FinFET. http://www.eda.org/edps/

the_floating_ gate
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
the_floating_ gate   4/16/2013 4:23:19 AM
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Who does direct write? ASML bought SVG and ASML killed it. Direct write goes back to Eaton? SUMMARY OF THE INVENTION An object of the present invention is to provide an improved electron beam lithography method for creating an exposure pattern having unprecedented resolution in an electron sensitive surface. This is accomplished in accordance with this invention by patternwise treating an electron sensitive surface to a high resolution pattern of low-energy electrons rather than high-energy electrons. ....... When the separation between the pointed electrode and the surface being treated is less than about 1 nm, the electron clouds of the atoms at the apex of the pointed electrode and at the surface opposite the apex touch, and a tunnel current path is established between the apex of the pointed electrode and the surface. When the separation is more than about 3 nm, electrons must leave the pointed source via field emission. When the separation is between about 1 and 3 nm, both current effects are experienced. In any case, the area of the surface receiving the electrons has a diameter roughly equal to the distance between the point source of the electrons and the target surface.

Diogenes53
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Diogenes53   4/21/2013 4:27:15 PM
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Burn Lin should have retired as the Holy Father of Immersion, basically saving an industry which made another obviously foolish bet on X-ray lithography (oh, sorry: EUV lithography) and while saving us from a 157nm black hole. The trouble with such success is it can breed hubris. Lin's E-beam direct write has had a similar history to X-ray. The end of optical seems around the corner, billions are spent on alternatives, all fail; now, the end of optical seems even closer, so the failures are renamed (EUV and maskless), more resources are wasted, but Mother Nature doesn't pay attention to marketing-created name-changes. Refocusing from X-ray to EBDW means instead of the overwhelming challenges of source, resist, and mask/blank, we have the overwhelming challenges of source, resist, throughput, and data path.

Mickey.Taiwan
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
Mickey.Taiwan   5/4/2013 4:12:19 AM
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God closes a door (optical lithography), he opens a widow for those who are with perseverance. It takes time and let's see.

resistion
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
resistion   5/4/2013 5:22:58 AM
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Optical is not ending, there's perseverance there as well.

resistion
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
resistion   5/4/2013 2:34:19 PM
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God also gave electrons mean free paths, so I doubt EUV or E-beam are the intended windows for lithography. http://www.google.com.tw/imgres?imgurl=http://www.virginia.edu/ep/SurfaceScience/mfp-luth.GIF&imgrefurl=http://www.virginia.edu/ep/SurfaceScience/diffract.html&h=1306&w=1760&sz=44&tbnid=QKsyadnm5B9OOM:&tbnh=92&tbnw=124&prev=/search%3Fq%3Delectron%2Bmean%2Bfree%2Bpath%26tbm%3Disch%26tbo%3Du&zoom=1&q=electron+mean+free+path&usg=__bB9cU--iCG-n29qsTr83sRrdjcg=&docid=jwiPBTm96sPScM&sa=X&ei=RRuFUdKrEM2jkQXxsYH4Cg&ved=0CDsQ9QEwAw&dur=156

double-o-nothing
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
double-o-nothing   5/5/2013 2:12:07 AM
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"Even if EUV hits its targets, the 10nm node also requires use of self-aligning techniques with immersion lithography to minimize the need for EUV to just some critical layers. TSMC also is developing a so-called G-rule that automates the tricky process of handling color conflicts in double patterning." It would be implied that no EUV layers would be best otherwise why all the trouble with the double patterning.

resistion
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re: TSMC starts FinFETs in 2013, tries EUV at 10 nm
resistion   6/2/2013 9:43:50 AM
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EUV source wall-plug power is 0.5 megawatt. Crazy. http://semimd.com/watts/2013/03/14/cymer’s-euv-team-has-an-exciting-few-months/

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