PARIS – Will fully depleted silicon on insulator (FDSOI) become a viable alternative to FinFET?
Semiconductor industry insiders have been asking this question for months. FDSOI, is an approach that supposedly delivers the benefits of reduced silicon geometries while enabling a simplification of the manufacturing process.
So far, STMicroelectronics was viewed as the only company tilting at the FDSOI windmill.
That perception, and a lonely market landscape, are about to change.
Since ST last week announced three design wins from its unnamed FDSOI customers, evidence is mounting for the emergence of an FDSOI “ecosystem.” The momentum is slowly but surely building on a global scale, extending from Europe to Japan and China.
Beyond ST, companies on the FDSOI bandwagon today include IBM, GlobalFoundries, design service companies such as VeriSilicon (Shanghai) and unnamed chip companies in Japan.
Of course, it can be argued that today’s emergent industry trend is not the “proof” of how well the finished system using an FDSOI-based processor might function. Rather, it’s evidence for the industry momentum that’s now propelling FDSOI.
But FDSOI at the current 28-nm node, and especially at future nodes like 14 nm, will have far-reaching ramifications in the semiconductor market of the future. As Dan Hutcheson, CEO of VLSI Research Inc., noted, “If FDSOI really does prove to be a competitive advantage at 14 nm, there could be an upset throughout the fabless/foundry supply chain, with GlobalFoundries and its customers coming out on top.”
That, of course, is not a given.
Betting against the semiconductor technology leaders such as Intel Corp. and Taiwan Semiconductor Manufacturing Corp., who are throwing a lot of money at FinFETs, is rarely a wise course of action.
Indeed, many chip companies today are still cooling their jets on FDSOI, or at least avoiding public comment. The financial community isn’t exactly pulling for the idea of FDSOI, either. If questions posed at ST’s financial analyst meeting last week in London are any indication, financial analysts were clearly wary of ST, which is not letting go of its manufacturing ambitions and its pursuit of FDSOI technology.
That said, industry/technology analysts are agreed on the following.
“FDSOI is plan B for chip vendors because it is far easier to execute than FinFET,” said VLSI Research’s Hutcheson. “Planar CMOS is likely to have too high a leakage and will need a lot of transistor engineering to overcome its speed and power deficits.”
There are a number of pros and cons when FDSOI is discussed partly because the core issues associated with FDSOI are not properly addressed. One of the critical issues with FDSOI is its scalerbility. According to device theory the SOI thickness or transistor channel thickness required to suppress transistor leakage current or short channel effect is 7nm for 28nm node, 3.5nm for 14nm node and 2.5nm for 10nm node. Soitec, the largest SOI wafer manufacturer, announced at 2011 SOI conference that what it can deliver in volume manufacturing are minimum 12nm SOI and 25nm UTBB(ultrathin buried oxide), meaning that ST has to thin down 12nm SOI to obtain the final 7nm SOI uniformly and reliably across 350mm wafers. If ST' FDSOI is superior to planer bulk 28nm and is available today as ST claims, why ARMH and Qulcomm's Snapdragon chips are manufactured for over two years by TSMC, but not by ST? 14nm and 10nm FDSOI require the SOI thickness of 3.5nm and 2.5nm, respectively. Such thin FDSOI not only physically can't be manufactured but also subject to so called quantum confinement or device physics limit. Therefore, ST's 14nm node will be the end of FDSOI scaling. On the other hand, FinFET will be extended to 4nm node because the fin width that is equivalent to SOI thickness requires 4nm in order to suppress the transistor leakage current. 4nm is equal to the gate length in this case. Furthermore, Intel's FinFET doesn't rely on Soitec wafers. Therefore, FDSOI can't be a viable alternative to FinFET. SKim
Can somebody explain why FDSOI 20nm can be in the same cost range as bulk CMOS? where did $400-500 wafer cost delta go? Is there fundamental processes,design assumption initiated doing this comparison? Performance is one thing, cost is a different issue. this can always be used for extreme low power application, which can tolerate higher pricing.
Unless the yield can reach 80% robustly, even such cost analysis doesn't mean much for die cost if it targetted for general mobile phone applications.
The industry in Japan actually has very deep FDSOI roots. Nobuyuki SUGII's (then) Hitachi team had a break-through paper at IEDM in 2008 “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” -- but they called it SOTB, so people might not realize it is indeed planar FD-SOI. Dr. Sugii first wrote about it for ASN in 2009 (http://www.advancedsubstratenews.com/2009/05/less-than-ever/), and in 2010 argued that the benefits would even be there for nodes as far back as 40/65nm (where there's still plenty of business see http://eda360insider.wordpress.com/2011/09/07/where-is-the-mainstream-ic-process-technology-today-28nm-40nm-65nm/). See Dr. Sugii's piece making the argument for the older nodes at http://www.advancedsubstratenews.com/2010/07/the-moment-is-now/. So in short, they might not need much convincing!
For those looking for more FDSOI info, the Consortium's got a huge amount -- see www.soiconsortium.org.
this article reminded me of grade-school social blather: X saw Y kissing Z at the party... couldn't we have a genuinely informative article on what properties fdsoi brings, how much trouble it'll cause, etc.
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