LONDON – Processor IP licensor ARM Holdings plc has announced the addition of cache coherency to the AMBA 4 interface and protocol specification that supports communications between cores.
The AMBA 4 specification now features AXI coherency extensions (ACE) in support of multicore computing. The so-called ACE specification enables system-level cache coherency across clusters of multicore processors, such as the Cortex-A15 MPCore processors and Mali-T604 graphics processors, ARM (Cambridge, England) said.
ARM has worked on the AMBA 4 revision of its on-chip communications protocol with a group of other companies that include: Arteris, Cadence, Jasper, Marvell, Mentor, Sonics, ST Ericsson, Synopsys and Xilinx.
Publishing a standard way of managing cache coherency, memory barriers and virtual memory management will reduce software cache maintenance, save processor cycles and reduce external memory accesses, ARM claimed.
The latest specification represents the second phase of the AMBA 4 protocol. Phase one of the AMBA 4 specification, launched in 2010, included definition of an expanded family of AXI interconnect protocols.
"As one of the first licensees of the ARM CoreLink CCI-400 Cache Coherent Interconnect, we welcome the introduction of the AMBA 4 ACE specification which will enable our energy-efficient high performance wireless platforms to exploit the full potential of heterogeneous multiprocessing," said Jim Nicholas, vice president & general manager of processor subsystems & product lifecycle management at ST-Ericsson, in a statement issued by ARM.
This could help ARM licensees save time and money develing heterogeneous multicore SoCs that use multiple versions of ARM, grahics and other cores--if they use this tech. I fear many may go their own ways. Note the biggest licensees--Nvidia, Qualcomm, TI--are NOT here. Also it would have been a HUGE win if an AMD for example would have adopted this for its hetero X86/graphics chips. That's a lot to ask but would lead to faster time to market and smooth the path for software developers who have their work cut out for them learning the underpinings of many multicore SoCs.
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