Breaking News
Research

IMEC benchmarks FinFET superiority

6/16/2011 11:59 AM EDT
2 comments
NO RATINGS
More Related Links
View Comments: Newest First | Oldest First | Threaded View
myogi
User Rank
Rookie
re: IMEC benchmarks FinFET superiority
myogi   6/22/2011 7:29:14 AM
NO RATINGS
To add on jnhong's comment, one might question the relevance of the exercise if the gate length is indeed 50nm.

jnhong
User Rank
Rookie
re: IMEC benchmarks FinFET superiority
jnhong   6/16/2011 9:10:06 PM
NO RATINGS
Layout looks very good, and extremely clean. But if that 500 nm dimension line is correct, the overall bitcell size is approx. 0.80 um by 3.5 um. That corresponds more closely to the 90 nm node's bitcell size.

August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
5 comments
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll
Radio
LATEST ARCHIVED BROADCAST
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.