LONDON – The IMEC research institute has compared one planar and two FinFET technologies to see how they perform against scaling and process variability.
The benchmark circuits were six-transistor SRAM cells and SRAM arrays and IMEC has concluded that the FinFET outperforms planar CMOS in variability-aware and technology-aware comparison of SRAM product yield.
Both FinFET on bulk and FinFET on silicon-on-insulaor (SOIFF) technologies come out superior to the planar technology for medium- to large-sized SRAM arrays resulting in higher yields, IMEC said although it did not disclose the process geometry at which the tests were done. It is likely to have been at around 28-nm to 22-nm.
As the dimensions of devices scale down, the variations in the electrical parameters of CMOS transistors steadily increase. This is due to random fluctuations in the density of the dopants in the channel, source and drain. So, two closely placed transistors that are supposedly identical can show a widely different behavior. This makes the design of SRAM memory cells less predictable and controllable for every new technology node.
Because of this scaling 6T planar SRAMs below 22-nm remains challenging, IMEC said. FinFET devices show a lower leakage and variability and it is possible to design more compact cells.
Both FinFET technologies come out as superior to planar for SRAM arrays of greater than 128-kbytes. They are less sensitive to mismatches, thus allowing a more aggressive scaling of the power supply and a lower VCC than planar arrays. For undoped silicon-on-insulator FinFETs (SOIFF), the power supply can be lowered by an additional 200-mV compared to planar. As a sample result: undoped SOIFF FinFET allow for a 95 percent yield at 0.7-V in 32-Mbit SRAM arrays, moving to Gbit arrays for higher voltages.
Layout looks very good, and extremely clean. But if that 500 nm dimension line is correct, the overall bitcell size is approx. 0.80 um by 3.5 um. That corresponds more closely to the 90 nm node's bitcell size.
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