LONDON – Researchers from Samsung Electronics Co. Ltd. are set to unveil the company's upcoming 20-nm logic process at the International Electron Devices Meeting (IEDM), which is due to take place in Washington DC, Dec. 5 to 7, 2011.
The process technology is planar, made using standard bulk CMOS, and does not include FinFETs, where the material around the transistor is etched away to leave the transistor in a fin-like structure.
Intel Corp., the world's largest semiconductor company, is already ramping its 22-nm manufacturing process technology, which is based on FinFETs, or tri-gate transistors as Intel calls them. Samsung and Taiwan Semiconductor Manufacturing Co. Ltd., rival chip manufacturers to Intel at the leading edge, are not expected to adopt the FinFET approach until the 14-nm generation of manufacturing.
Therefore the attributes of the planar 20-nm process and how quickly Samsung can roll it out are key to determining how much of a manufacturing lead Intel has over the rest of the industry.
In the IEDM paper, for which the organizers have released an abstract, Samsung researchers are set to report on device structures operating at 0.9V with drive currents of 770-microamp per micron for the n-type FET and 756-microamps per micron for the p-type FET. A six-transistor SRAM bit cell is among the structures built using the process and Samsung is expected to report a static noise margin of 250mV at the operating voltage of 0.9V.
The planar process includes high-k/metal gate (HKMG) and strain engineering, as expected and is intended to offer low power AND high performance, according to the abstract. The gate-pitch is 80-nm gate offering a high gate density.
Paper 15.1, Bulk Planar 20-nm High-k/Metal Gate CMOS Technology Platform for Low-Power and High-Performance Applications, H.J. Cho et al., Samsung
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