LONDON – The full program of the International Electron Devices Meeting has been posted online and it reveals that there are continuing strands of research into phase-change memory at Samsung and a promising alliance between Macronix and IBM. These strands are in addition to research at Hynix Semiconductor Inc. which is due to be reported at IEDM as having caught up with the state of the art by detailing a 1-Gbit memory on a 42-nm process.
The non-volatile phase-change memory technology, long discussed as an alternative active memories and flash, is contentious because despite many years of research by numerous companies it has yet to reach the market in any notable volumes.
Nonetheless a Samsung research team is scheduled to lead off an IEDM session dedicated to PCM and resistive RAM by presenting a fully integrated 20-nm phase-change random access memory cell. The cell includes novel bottom electrode materials that were developed to get the reset current below 100-microamps, according to the IEDM advanced program. The same team has been invited to give a paper on data retention, cycling endurance and write disturbance in PCM which appears at the end of session 12 on yield and reliability.
Meanwhile researchers from Macronix International Co. Ltd. and the IBM T.J.Watson Research Center are slated to present three papers. Paper 3.2 is on 39-nm device structure with a 30-microamp reset current and 10^9 cycling endurance. The team used the poor thermal conductivity of TaN in an under-electrode thermal barrier. The 30-micro-amp reset current is said to be a 90 percent reduction from previous lows.
In paper 3.4 a research team drawn from Macronix and IBM is set to talk about exploring the mixes of germanium-antimony-tellurium (GeSbTe) or GST and finding a material superior to GST-225. The switching speed is similar to undoped GST-225, but with 30 percent lower reset current, and nearly 100 degree C higher transition temperature, and thus much better thermal stability, the abstract states.
Macronix and IBM have gone further and produced a 128-Mbit device and are due to report test results at both the wafer level and for packaged dies. The abstract states that the devices have shown 10^8 (100 million) endurance cycling and withstood temperature up to 190 degrees C.
The IEDM is due take place in Washington DC on Dec. 5 to 7, 2011.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.