LONDON – Startup SuVolta Inc. has announced that its novel transistor technology, dubbed PowerShrink, operates down to 0.425-V, approximately 300-mV below conventional processes. PowerShrink is based on a deeply depleted channel (DDC) transistor manufactured in epitixially grown doped silicon on the surface of a conventional bulk CMOS wafer.
The progress is set to be discussed in a paper due to be presented at the International Electron Device Meeting presented by a researcher from Fujitsu Semiconductor Ltd.
The paper entitled: Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications, is co-authored by Fujitsu and SuVolta (Los Gatos, Calif.).
The reduction in variation is important because leakage current in transistors is exponentially dependent on VT and power dissipation is dominated by the low edge of the VT distribution. The tighter the distribution the lower the VT can be set.
Fujitsu has demonstrated low voltage operation of a 576-kbit SRAM block based on SuVolta's PowerShrink implemented in a 65-nm CMOS process technology. SuVolta is pitching PowerShrink as an alternative to both FinFETs and fully depleted SOI (FDSOI) which are generally considered to be the major strands of process technology beyond 22-nm. Intel has already introduced a FinFET process technology.
SuVolta's is hoping that publicly disclosed progress by Fujitsu will help persuade process research groups that its approach is superior to FinFET in that it more easily supports multiple threshold voltages over a wider voltage range, and lower cost than FDSOI in that it does not require premium-priced SOI wafers as its starting point.
SuVolta continues to come up with very exciting announcements...but how one develops very advanced transistor structures without access to a state-of-the-art fab?...was the work done at Fujitsu's facilities? Kris
I don't think it is made explicit exactly where the work was done. But I think it is safe to assume it was done at a Fujitsu wafer fab or research fab where they can run the 65-nm CMOS manufacturing process.
thank you Peter...low VDD operation requires low VTH...but a textbook challenge of lowering VTH is increased leakage current (it is an exponential increase), perhaps someone from SuVolta can explain how they have overcome that challenge...Kris
My understanding is that the text book challenge to increased leakage current in bulk CMOS is because of the depth of the transistor channel
Like FinFET and FDSOI, DDC has a shallow and tightly controlled channel. Unlike FinFET DDC can support multiple VTs easily.
thank you @agk...static body bias would just shift VTH permanently so it will not solve anything...how would dynamic bias work? low VTH when in operation and high VTH when powered off?...I thought the same trick is used in many processes (like SOI for example)...Kris
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