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MIT makes Hornet multicore simulator power aware

3/9/2012 12:48 PM EST
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doubee
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re: MIT makes Hornet multicore simulator power aware
doubee   3/12/2012 10:42:55 PM
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http://people.csail.mit.edu/devadas/pubs/nocs-2011-final.pdf Impressive work, but this is a trace-driven simulation, i.e., the core memory traffic is simulated separately and replayed in Hornet. This inherently affects the accuracy of the program because the cores' instruction traces do not reflect contention due to hotspots in the network, etc. Most cycle-accurate simulators today are SLOW to begin with because a) they model the cycle-by-cycle timing of actual out-of-order processors, and b) they are execution-driven, requiring a round-trip evaluation of all the timing delays propagated throughout the memory system and network, which must be fed back to delaying the stepping of the cores. This process is inherently difficult to parallelize.

Kinnar
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re: MIT makes Hornet multicore simulator power aware
Kinnar   3/11/2012 7:39:02 AM
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It is good that a university has founded this project, it will provide an opportunity to the other country researchers to work upon it being open license, in future this will be area here most of the potential of the researchers will be used.

t.alex
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re: MIT makes Hornet multicore simulator power aware
t.alex   3/10/2012 2:16:50 PM
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Is there any demo of this?

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