LONDON – Nick Kepler, vice president of products at startup company SuVolta Inc. (Los Gatos, Calif.), has authored an article that expounds the virtues of his company's deeply depleted channel (DDC) technology as a life extender for established bulk CMOS manufacturing nodes such as 90- and 65-nm (see Rethinking the pursuit of Moore's Law).
Kepler argues that the application of DDC and voltage reduction to 65-nm CMOS can produce a lower power consumption device on a lower cost die than the same design implemented in 28-nm bulk CMOS. This conclusion is reached even though the 28-nm die would be roughly half the size of the same IC design in 65-nm CMOS.
DDC uses tight control of graded dopant concentrations below the transistor channel to produce similar results to FinFET physical geometry and FDSOI wafers. The two primary benefits claimed for DDC are a tighter control of the variation in threshold voltage and lower voltage operation. SuVolta's DDC CMOS transistor technology takes both of these approaches to reduce the power consumption of CMOS ICs by 50 percent or more while maintaining performance at a given manufacturing node, the company has claimed.
The early disclosure of the technology at IEDM in 2011 pitched the technology as an easier to implement, lower cost alternative to both FinFETs and FDSOI, generally considered the two major strands of process technology at 22-nm and beyond. This was even though much of the DDC R&D was done in collaboration with Fujitsu Ltd using a 65-nm bulk CMOS baseline process.
Kepler's article argues that the non-recurring engineering costs, including design IP and masks costs, are five times more expensive at 28-nm as they are at 65-nm. However, the article does not factor in additional wafer engineering costs for the DDC process, nor explain a predicted escalation in per-die cost despite die size reduction.
The given conclusion is that the majority of ICs would benefit from remaining on mature process technologies because of the high costs associated with migrating to leading-edge manufacturing processes. DDC brings the option of reducing the power consumption of designs while delaying migration to finer geometries until the steep portion of the cost-learning curve is past. Kepler also makes the point that migration to the 28-nm and 20-nm nodes migration will be particularly expensive because of the need for double patterning of structures, doubling mask cost and increasing dwell time on machines in the wafer fab.
"This technology extension benefit will remain true as the specific process technologies that are classified as “mature” (90nm and 65nm today) and “leading-edge” (28nm today) change over time," Kepler concluded. No disclosure is made as to whether Fujitsu or any other chip manufacturer or foundry has plans to introduce low power consumption DDC versions of established bulk CMOS processes.
Nvidia made related comments. We can debate the node 20? 14? But transistor cost even at maturity is not really lower at some point. So that begs the question why pay for higher cost for a few years just to get to cost parity?
Even at the 20nm node our company thinking was 20nm MIGHT only make sense for application processors chips. All other chips like wifi, we think will stay at 40/28nm. Interesting that even Nvida questions value of 20nm? They have historically been 1st movers and helped bebug yield and design rule issues to help make 65 /45/40 viable for industry.
seems right . For more and more of our product line, ROI is staying at mature node longer and moving to advanced node later. If mature node is improved more, even better.
At a high level this is driven by the increasing cost of the advance node plus the advanced node delievering less "goodness" over time.
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