LONDON – Chip giant Intel and the research partnership clustered around IBM and STMicroelectronics are each set to report progress on their approaches to leading-edge IC manufacturing during the International Electron Devices Meeting (IEDM) in San Francisco in December.
Research teams are set to present on the FinFET approach--called tri-gate by Intel--on fully-depleted silicon-on-insulator (FDSOI) and on bulk planar processes at around 20 nm and beyond.
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Intel is set to deliver a paper on its 22-nm FinFET technology for SoC applications. In the same session, a research team drawn from CEA-Leti, STMicroelectronics, IBM, Globalfoundries and Renesas will present a paper on ultra-thin box and body (UTBB) FDSOI transistors for a multiple threshold voltage strategy at 20 nm and below.
ST will also report on switching energy efficiency in the UTTB process while IBM will describe a 22-nm SOI process. Meanwhile, Samsung researchers will deliver a research paper on the extensibility of its bulk 20-nm planar HKMG process.
Intel is already making processors using a 22-nm FinFET manufacturing process technology. It has described that process as a CPU process that was not optimized for lowest power consumption whereas the subject of the IEDM presentation is called an SoC process. Intel will provide engineering details of its 22-nm tri-gate SoC process and discuss its use of the approach to build a technology platform for SoC applications. That implies broad families of high-speed, low standby power and high voltage tolerant transistors, as well as RF and mixed-signal capabilities, according to the paper's abstract.
High-speed logic transistors have sub-threshold leakages ranging from 100-nA per micron to 1-nA per micron, while the low-power versions feature a leakage of less than 50-pA per micron. Nonetheless, the process retains 1.8- and 3.3-volt transistors for analog circuits, and legacy circuits.
The Intel 22-nm SoC platform also includes carbon-doped oxide interconnect and three different types of SRAM bit cell to provide options between density, performance and low voltage operation, according to the the abstract.
In another session on Dec. 11, a paper authored by a team from IBM, STMicroelectronics, Globalfoundries, Renesas, Soitec and CEA-Leti will report on another SOI process at 22-nm known as ETSOI for extremely thin silicon-on-insulator. This process has a silicon channel for n-type transistors and strained silicon-germanium channel for p-type transistors.
IEDM runs from Dec. 10 to 12 at the Hilton San Francisco Union Square.
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