LONDON – Chip giant Intel and the research partnership clustered around IBM and STMicroelectronics are each set to report progress on their approaches to leading-edge IC manufacturing during the International Electron Devices Meeting (IEDM) in San Francisco in December.
Research teams are set to present on the FinFET approach--called tri-gate by Intel--on fully-depleted silicon-on-insulator (FDSOI) and on bulk planar processes at around 20 nm and beyond.
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Intel is set to deliver a paper on its 22-nm FinFET technology for SoC applications. In the same session, a research team drawn from CEA-Leti, STMicroelectronics, IBM, Globalfoundries and Renesas will present a paper on ultra-thin box and body (UTBB) FDSOI transistors for a multiple threshold voltage strategy at 20 nm and below.
ST will also report on switching energy efficiency in the UTTB process while IBM will describe a 22-nm SOI process. Meanwhile, Samsung researchers will deliver a research paper on the extensibility of its bulk 20-nm planar HKMG process.
Intel is already making processors using a 22-nm FinFET manufacturing process technology. It has described that process as a CPU process that was not optimized for lowest power consumption whereas the subject of the IEDM presentation is called an SoC process. Intel will provide engineering details of its 22-nm tri-gate SoC process and discuss its use of the approach to build a technology platform for SoC applications. That implies broad families of high-speed, low standby power and high voltage tolerant transistors, as well as RF and mixed-signal capabilities, according to the paper's abstract.
High-speed logic transistors have sub-threshold leakages ranging from 100-nA per micron to 1-nA per micron, while the low-power versions feature a leakage of less than 50-pA per micron. Nonetheless, the process retains 1.8- and 3.3-volt transistors for analog circuits, and legacy circuits.
The Intel 22-nm SoC platform also includes carbon-doped oxide interconnect and three different types of SRAM bit cell to provide options between density, performance and low voltage operation, according to the the abstract.
In another session on Dec. 11, a paper authored by a team from IBM, STMicroelectronics, Globalfoundries, Renesas, Soitec and CEA-Leti will report on another SOI process at 22-nm known as ETSOI for extremely thin silicon-on-insulator. This process has a silicon channel for n-type transistors and strained silicon-germanium channel for p-type transistors.
IEDM runs from Dec. 10 to 12 at the Hilton San Francisco Union Square.
I am little confused by the title “Intel, Rivals gird for IC manufacturing showdown” because IEDM (International Electron Device Meeting) has not been a forum for IC manufacturing showdown, instead mainly for new research devices, new transistor analysis techniques, device physics, scaling limits…etc. Furthermore, among the three major technologies for 22/20 nodes, FDFinFETs by Intel, FDSOI/UTTBB by IBM Alliances and planar bulk Si by Samsung to be presented here at IEDM, Intel is the only one manufacturing its FDFinFETs for several months now. IBM and Samsung have not announced yet when their technologies will be manufacturing. Therefore, in my opinion the word manufacturability would be more appropriate than “manufacturing” because manufactrability will become the determining factor for ultimate CMOS scaling for 22/20nm nodes and beyond. In order to have manufacturability assessments the transistor electrical characteristics such as VT, dId/dVg, dId/dVd, DIBL, and SS (sub-threshold slope) should be measured, and used also as minimum criteria for paper selection. I have been attending IEDM for over ten years. The paper selection has significantly deteriorated recently as indicated by a significant number of the papers presented don’t meet the minimum criteria. Skim
So why not mix and match these techniques using the best for the type of circuits.
Finfets for fast transievers with power gating when not in use. Others that do not need the speed or low power switching can be other types.
I was drawing finfets in my notebook in the early 90's sitting in ee classes.
Mike Bruzzone is fm IBM PC Board add on’s; Turbo, Memory, Network Card, 1st 2.5 D PC AT graphics card, 33 PC introductions including fastest 386 33 class workstation on memory write back; co host 1990 SIGGRAPH, first PC Standard MP C&T Corallary Chip set, first not Intel 387 math coprocessor, first not Intel 486SLC/486DLC, 486S Intel substitute microprocessors, first Nx586 replacement platform, first 16 bit bus 32 bit core Mini RISC, first 32 bit performance Mini RISC SOC, first I frame editor, first fast486120, some Alpha&NT, first low power C6 desktop & first less than $1,000 PC. Current research tracks include economics of fabrication; member Silicon Valley Round Table, intersection x86 & ARM, HPC/GPU/APU, resistive RAMs & advanced non volatile memory structures.
Mike Bruzzone is an Intel competitive strategist specializing in not Intel product commercialization who is invited discovery technical assistant by Federal Trade Commission Bureau of Competition for FTC v Intel Docket 9288, lettered to work report Assistant AG Antitrust Division of the State of California Department of Justice for defining Sherman Act Section One violation, a EUCC domestic U.S point of contact Monti/Kroes/Martinez Commissions, SEC recognized Relator by letter, Federal False Claims Act Original Source by letter U.S. Attorney Northern California District, recognized Relator Intel monopoly procurement theft in fifty States, four territories and the District of Columbia, invited discovery technical assistant FTC Chairman Referral back into Bureau of Competition Docket 9341, FBI original source of Intel Dealing Cartel 1996.
Criminal sub groups operating in Intel have in past positioned detractors as mentally ill, including their own employees up high in the enterprise who question Intel’s invented reality in pursuit of error correction, remedies, maintenance of democratic capitalism & industrial social responsibilities. For consultancy inquire email@example.com
Confirmed--Intel baseband will use foundry (mostly TSMC) for next 2-3 years since Intel's internal cost is too high. This is because Intel's 22nm to get to yield has more restrictive design rules (increases die size). Restrictive design rules are on logic, analog, I/O, and back-end metal. Intel will never have competitive baseband chips in its 22nm SOC.
Same is true for Intel's atom line, 22nm SOC Intel chip name Valleyview)...it is that part again due to the restrictive design rules that will not be competitive on cost.
I hope your foundry contact is an ex-intel guy and he knows what he is comparing to. Most likely he is comparing what their FINFET will be in the COST sense. I will never doubt Intel's manufacturing cost much or significantly lower than foundry offering. Intel's biggest expense might not be in wafer manufacturing, they also need to cover IP/EDA tool development/product design teams, in addition marketing cost..... You should consider Synopsys/Candence/ARM/Virage../TSMC/SPIL/ASE../Qualcomm/nVidia.... before you start calculating the selling price. Too bad Intel can't just open its technology/manufacturing capability for design houses. You might want to check the baseband/AP SOC chips Clover Trail are made at TSMC or not? How about even 32nm SOC Medfield chip in TSMC? Who cares about legacy chips at TSMC? Also x86 atom is in the range 20x2 =40 price range. Nobody is using server chip for mobile phone. The war is getting more excited finally.
Intel cannot afford to implement beyond 20nm. SandyBridge Moble Mfg Cost $0.40 per sq mil dice area.
US Government & Intel are concealing Corp. is looted by employees and stakeholders & Bankrupt in future terms.
5 Sources; 1) infiltration by cartel organized network crime; 2) banked cost constructing surplus barrier limiting competitors beyond 32 nm; 3rd, theft from stockholder’s administers cost of channel price fix tie; 4th, theft fm end customers charged price fix in invoice plus monopoly overcharges. Likely PC end buyers will see some recovery. 5th industrial theft processors dumped at price less than cost. 5 categories record $178,713,547,976 misrepresented & unreported cost burden on Intel.
Where are present cost burdens? 1st, inventories Xeon Westmere EX, Aarondale, Sandy Bridge Desktop & Mobile. 3 Issues; first, surplus processors banked in channels on deferred revenue recognition; 2nd, completed systems stalled in channels showing now what is occurring inside Intel; 3rd, surplus banked goods; processors, systems, repurposed for apps that will compete against Intel future product placing burden on industry in total.
Finally, one must ask why Intel is sustaining price on prior runs instead of flushing at cost to recover investment burden?
For Intel to dump inventories means twin tower effect on supply chain. Processor margins eliminated AMD becomes system house to capture remaining downstream producer values. Same for other processor design producers impacted by surplus raining down.
Collapse flattens Intel’s long time channel & contract manufacturers finally take over for certain.
Final question was price hold a hidden condition in Docket 9341 consent agreement? It’s time for regulatory mechanisms in this country that are supposed to police monopolization, cartel and investment fraud, including at Intel, to do that job of be replaced with administrations that will do that job.