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Process showdown set for IEDM conference

9/24/2012 05:00 PM EDT
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chipguy 1
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re: Process showdown set for IEDM conference
chipguy 1   9/24/2012 7:59:24 PM
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My foundry contact has studied Intel's 22nm SOC FinFET manufacturing flow and claims that it is not cost effective (compared to foundry 28nm/32nm) to manufacture mobile chips hence even Intel over next 3 years will still make most of its Infineon mobile cell phone chipsets at TSMC. Chips such as the 2 main chips in Apple's iphone 5: MDM9615 and A6 have an average ASP of $20 compared to similar die size X86 that Intel sells for $100-200)

PHW_#1
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re: Process showdown set for IEDM conference
PHW_#1   9/26/2012 8:13:31 AM
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I hope your foundry contact is an ex-intel guy and he knows what he is comparing to. Most likely he is comparing what their FINFET will be in the COST sense. I will never doubt Intel's manufacturing cost much or significantly lower than foundry offering. Intel's biggest expense might not be in wafer manufacturing, they also need to cover IP/EDA tool development/product design teams, in addition marketing cost..... You should consider Synopsys/Candence/ARM/Virage../TSMC/SPIL/ASE../Qualcomm/nVidia.... before you start calculating the selling price. Too bad Intel can't just open its technology/manufacturing capability for design houses. You might want to check the baseband/AP SOC chips Clover Trail are made at TSMC or not? How about even 32nm SOC Medfield chip in TSMC? Who cares about legacy chips at TSMC? Also x86 atom is in the range 20x2 =40 price range. Nobody is using server chip for mobile phone. The war is getting more excited finally.

James7740
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re: Process showdown set for IEDM conference
James7740   9/24/2012 11:13:39 PM
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Peter, I have seen others post this as well. Can you address why repeating the intel spin on "manufacturing show down" makes any sense when today most advanced atom SOC is on 32nm and will stay that way until end of 2013 ! while Qualcomm is shipping 50M units 28nm this year in just the iPhone 5 design alone and (2) I thought all you guys were writing about intel winning mobile market with 22nm finfet last year (2011) and intel has not demo anything close to A6 CPU or graphic power/performance (at mobIle power level) .... Even demoed something close to what is already shipping !

Peter Clarke
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re: Process showdown set for IEDM conference
Peter Clarke   9/25/2012 10:00:23 AM
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@James I was not aware that Intel has a position on a "manufacturing show down" and therefore did not try to repeat it. My intention was to tell readers that papers will be presented at IEDM on many of the leading-edge process technologies that will be producing chips in the near future. And therefore San Francisco in early December would be a good place to find out more. The rigor of the IEDM review process means that these should be detailed, quantitative presentations albeit likely to be only on certain aspects of each of these processes. From my perusal of the program the 14-nm logic node is being discussed mainly by academic groups looking at aspects of doping and strain in individual transistors. To your second point. All what guys?

green_ee
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re: Process showdown set for IEDM conference
green_ee   9/25/2012 3:55:03 PM
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22nm not cost-effective ? I suppose that depends upon the level of integration. While it's probably not a cost-savings to replace small individual 32nm devices with 22nm, there is a definite cost-savings thru higher integration at smaller process geometries to reduce PCB area, total BOM, and possibly power-savings as well.

ANON1255185289979
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re: Process showdown set for IEDM conference
ANON1255185289979   9/25/2012 6:03:26 PM
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Will there be any discussion of planned process metrology?

Peter Clarke
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re: Process showdown set for IEDM conference
Peter Clarke   9/26/2012 9:30:33 AM
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I don't see any planned discussion of process metrology. Probably something for one of the Semicon conferences?

MClayton200
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re: Process showdown set for IEDM conference
MClayton200   9/26/2012 2:40:52 AM
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@bruzzer is this some innovative marketing statement? Who is the client.

rfab
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re: Process showdown set for IEDM conference
rfab   9/26/2012 10:52:34 AM
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Mike Bruzzone Should be mentally ill

chipguy 1
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re: Process showdown set for IEDM conference
chipguy 1   9/26/2012 2:00:13 PM
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PHW_#1, Confirmed--Intel baseband will use foundry (mostly TSMC) for next 2-3 years since Intel's internal cost is too high. This is because Intel's 22nm to get to yield has more restrictive design rules (increases die size). Restrictive design rules are on logic, analog, I/O, and back-end metal. Intel will never have competitive baseband chips in its 22nm SOC. Same is true for Intel's atom line, 22nm SOC Intel chip name Valleyview)...it is that part again due to the restrictive design rules that will not be competitive on cost.

I_B_GREEN
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re: Process showdown set for IEDM conference
I_B_GREEN   9/28/2012 2:49:23 PM
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So why not mix and match these techniques using the best for the type of circuits. Finfets for fast transievers with power gating when not in use. Others that do not need the speed or low power switching can be other types. I was drawing finfets in my notebook in the early 90's sitting in ee classes.

michigan0
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re: Process showdown set for IEDM conference
michigan0   10/4/2012 3:46:26 PM
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I am little confused by the title “Intel, Rivals gird for IC manufacturing showdown” because IEDM (International Electron Device Meeting) has not been a forum for IC manufacturing showdown, instead mainly for new research devices, new transistor analysis techniques, device physics, scaling limits…etc. Furthermore, among the three major technologies for 22/20 nodes, FDFinFETs by Intel, FDSOI/UTTBB by IBM Alliances and planar bulk Si by Samsung to be presented here at IEDM, Intel is the only one manufacturing its FDFinFETs for several months now. IBM and Samsung have not announced yet when their technologies will be manufacturing. Therefore, in my opinion the word manufacturability would be more appropriate than “manufacturing” because manufactrability will become the determining factor for ultimate CMOS scaling for 22/20nm nodes and beyond. In order to have manufacturability assessments the transistor electrical characteristics such as VT, dId/dVg, dId/dVd, DIBL, and SS (sub-threshold slope) should be measured, and used also as minimum criteria for paper selection. I have been attending IEDM for over ten years. The paper selection has significantly deteriorated recently as indicated by a significant number of the papers presented don’t meet the minimum criteria. Skim

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