LONDON – Chip giant Intel and the research partnership clustered around IBM and STMicroelectronics are each set to report progress on their approaches to leading-edge IC manufacturing during the International Electron Devices Meeting (IEDM) in San Francisco in December.
Research teams are set to present on the FinFET approach--called tri-gate by Intel--on fully-depleted silicon-on-insulator (FDSOI) and on bulk planar processes at around 20 nm and beyond.
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Intel is set to deliver a paper on its 22-nm FinFET technology for SoC applications. In the same session, a research team drawn from CEA-Leti, STMicroelectronics, IBM, Globalfoundries and Renesas will present a paper on ultra-thin box and body (UTBB) FDSOI transistors for a multiple threshold voltage strategy at 20 nm and below.
ST will also report on switching energy efficiency in the UTTB process while IBM will describe a 22-nm SOI process. Meanwhile, Samsung researchers will deliver a research paper on the extensibility of its bulk 20-nm planar HKMG process.
Intel is already making processors using a 22-nm FinFET manufacturing process technology. It has described that process as a CPU process that was not optimized for lowest power consumption whereas the subject of the IEDM presentation is called an SoC process. Intel will provide engineering details of its 22-nm tri-gate SoC process and discuss its use of the approach to build a technology platform for SoC applications. That implies broad families of high-speed, low standby power and high voltage tolerant transistors, as well as RF and mixed-signal capabilities, according to the paper's abstract.
High-speed logic transistors have sub-threshold leakages ranging from 100-nA per micron to 1-nA per micron, while the low-power versions feature a leakage of less than 50-pA per micron. Nonetheless, the process retains 1.8- and 3.3-volt transistors for analog circuits, and legacy circuits.
The Intel 22-nm SoC platform also includes carbon-doped oxide interconnect and three different types of SRAM bit cell to provide options between density, performance and low voltage operation, according to the the abstract.
In another session on Dec. 11, a paper authored by a team from IBM, STMicroelectronics, Globalfoundries, Renesas, Soitec and CEA-Leti will report on another SOI process at 22-nm known as ETSOI for extremely thin silicon-on-insulator. This process has a silicon channel for n-type transistors and strained silicon-germanium channel for p-type transistors.
IEDM runs from Dec. 10 to 12 at the Hilton San Francisco Union Square.
22nm not cost-effective ? I suppose that depends upon the level of integration. While it's probably not a cost-savings to replace small individual 32nm devices with 22nm, there is a definite cost-savings thru higher integration at smaller process geometries to reduce PCB area, total BOM, and possibly power-savings as well.
I was not aware that Intel has a position on a "manufacturing show down" and therefore did not try to repeat it.
My intention was to tell readers that papers will be presented at IEDM on many of the leading-edge process technologies that will be producing chips in the near future. And therefore San Francisco in early December would be a good place to find out more.
The rigor of the IEDM review process means that these should be detailed, quantitative presentations albeit likely to be only on certain aspects of each of these processes.
From my perusal of the program the 14-nm logic node is being discussed mainly by academic groups looking at aspects of doping and strain in individual transistors.
To your second point. All what guys?
I have seen others post this as well. Can you address why repeating the intel spin on "manufacturing show down" makes any sense when today most advanced atom SOC is on 32nm and will stay that way until end of 2013 ! while Qualcomm is shipping 50M units 28nm this year in just the iPhone 5 design alone and
(2) I thought all you guys were writing about intel winning mobile market with 22nm finfet last year (2011) and intel has not demo anything close to A6 CPU or graphic power/performance (at mobIle power level) .... Even demoed something close to what is already shipping !
My foundry contact has studied Intel's 22nm SOC FinFET manufacturing flow and claims that it is not cost effective (compared to foundry 28nm/32nm) to manufacture mobile chips hence even Intel over next 3 years will still make most of its Infineon mobile cell phone chipsets at TSMC.
Chips such as the 2 main chips in Apple's iphone 5: MDM9615 and A6 have an average ASP of $20 compared to similar die size X86 that Intel sells for $100-200)
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.