Any doubts about the forward march to 90- and 65-nanometer geometries and multimillion-gate counts should be put to rest by the 339 ASIC and IC designers who responded to the EE Times/Deutsche Bank 2005 EDA survey.
The survey suggests that chip designers may be moving to lower-geometry nodes faster than some people might think. A full 28 percent said their current project is at 90 nm and 5 percent said they're working at 65 nm. In two years, those figures are expected to be 33 percent and 24 percent, respectively, with 6 percent working at 45 nm.
Despite the challenges of higher complexity, there's relatively little outsourcing of placement and routing or other IC design tasks. And despite the technology challenges at 90 nm and below, chip designers are more positive about EDA tool technology than they are about licensing, pricing and interoperability.
Design-for-manufacturability (DFM), a key theme at this week's Design Automation Conference, isn't very high on chip designers' list of current concerns, although it's seen as a problem that's getting worse. The greater concerns are the old standbys: timing closure, power and functional verification. A majority of respondents said they're using internal tools, but those are mostly scripts that control other tools.
The median gate count today is 2.4 million; in two years, that's expected to nearly double, to 4.2 million. Respondents expect that 36 percent of designs will be over 10 million gates in two years, with 8 percent over 100 million gates. Today's median maximum clock speed is 349 MHz, with 22 percent of respondents working at 1 GHz or above.
Memory and analog content is significant, as is intellectual-property (IP) reuse. On average, respondents said, 38 percent of the equivalent-logic gates are taken up by digital logic, 25 percent by memory and 20 percent by analog/RF. A total of 24 percent of equivalent-logic gates are taken up by IP blocks designed by others.
For current design projects, the expected time-to-market is 14 months and the mean cost $8.8 million, respondents said. The median cost is $2.1 million.
Respondents said that system-level design takes up 18 percent of the design cycle, RTL logic design 20 percent, functional verification 28 percent, synthesis 12 percent, and physical design and verification 26 percent. Vendor claims that verification takes 70 percent of the design cycle do not seem to be supported.
IC design appears to be compartmentalized and specialized no sign of the "tall, thin designer" who supposedly does it all. Twenty-four percent of respondents do architectural definition, 21 percent do RTL design, 21 percent do RTL verification, 18 percent do synthesis and 20 percent do placement and routing. Nowhere is there a single task done by 30, 40 or 50 percent of respondents, as is often the case with FPGA and pcb design.
The task most frequently given to third-party suppliers is IC place and route, but only 15 percent of respondents said their companies do that. Some 14 percent outsource physical verification, while 10 percent outsource analog or mixed-signal design. Only 2 percent outsource architectural definition.
A total of 39 percent of respondents said they outsource some portion of chip-level design: 90 percent to companies in North America, compared with 24 percent in India and 21 percent in China. The most frequent type of outsourcing partner is an independent design consultancy.
The three most critical issues for IC designers are meeting timing budgets, completing functional verification and meeting power budgets. But signal integrity, fourth on the list, is the challenge that's most notably getting worse as process nodes shrink. DFM is another challenge that's growing.
Items of least concern: IP selection/verification, tool interoperability and using all available gates. Some 60 percent of respondents said they're taking full advantage of the gate capability available at their current process node. Of those who aren't, time-to-market pressures and EDA tool limitations are the primary reasons.
A majority of respondents said their design groups use design-for-test, formal verification, physical synthesis, power analysis, functional coverage and RTL floor planning. A full 46 percent said they use statistical timing analysis, a surprising figure given the lack of commercial tools. Only 28 percent use SystemVerilog today, but 53 percent plan to within two years. A total of 33 percent plan to use SystemC within two years, compared with 17 percent today, and 22 percent plan to use C-language synthesis, compared with 13 percent today. These SystemC and C synthesis numbers suggest a growing interest in electronic system-level (ESL) design.
Asked to evaluate EDA tools, respondents said they are most satisfied with accuracy, handling large designs and EDA vendor support. It should be noted that only 40 percent said they were fully satisfied with accuracy, while 60 percent said it "could be better" or "needs improvement." Least satisfaction was with multivendor interoperability (18 percent), cost of purchase (15 percent) and cost of ownership (14 percent).
Satisfaction with individual tools was highest for simulation (47 percent) and synthesis (45 percent), lowest for power estimation (24 percent) and signal integrity (26 percent). Users were much less satisfied with hardware-assisted verification (28 percent) than with simulation or formal verification (41 percent).
A key part of the survey was the ranking of vendors. Respondents were first asked to check off vendors whose products they've used or purchased. No surprise with the top three: Cadence Design Systems Inc., Synopsys Inc. and Mentor Graphics Corp., at 83, 79 and 58 percent, respectively. The fourth most-cited vendor may come as a surprise to some: The Mathworks, creator of Matlab (32 percent). Then came Novas Software (25 percent), Synplicity (25 percent) and Magma Design Automation (22 percent). The top 10 were rounded off by Denali, Agilent EEsof, Logic Vision and Nassda, in that order.
Respondents were asked how satisfied they were with each vendor, using a five-point scale. Compiling results from the top two boxes, Novas came out first, with 78 percent. Among the top-three providers, Cadence drew satisfaction numbers of 51 percent, Synopsys 62 percent and Mentor 58 percent.
While 56 percent of respondents said they use internally developed tools, most of that tally involves scripts that drive other tools (81 percent). Some 35 percent use internal system-level modeling tools, while 24 percent use internal architectural-definition tools. Both are key targets of the emerging ESL providers.
Fully 82 percent of those surveyed agree strongly or somewhat with the statement "I prefer to buy from established vendors." Just over half 52 percent agree strongly or somewhat that "I'd consider buying from startups." But the statement that garnered the most "agree strongly" votes was "There's too much hype in product rollouts" (31 percent); the least, "Tools work as promised by vendors" (5 percent).
What about value? Nine percent agree strongly and 65 percent agree somewhat that "I get good value from my EDA vendors." Six percent agree strongly, and 55 percent agree somewhat, that "EDA licensing models work for me." The most frequently used model is a time-based license (TBL) of three years or less (53 percent). Perpetual follows at 43 percent. Asked what respondents most prefer, 35 percent chose perpetual, 27 percent TBLs of three years or less, 20 percent TBLs of three years or more and 17 percent project-based licensing.
In the space devoted to comments, the designers broadcast these messages: Reduce prices, give us more flexibility in licensing, improve quality and usability, and keep up with technology. "We need a better licensing model that can allow customer control of costs on an as-used basis," said one. "Do not neglect analog and older technologies," said another.
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