Synopsys Inc. and Xilinx Inc. are teaming up to bridge the design-flow gap between ASICs and high-end PLDs.
In a joint promotional and educational program, they will offer tools and technical know-how to help ASIC designers exploit the functionality and time-saving advantages of Xilinx's FPGAs.
Advances in PLD capacity and speed have made them increasingly attractive within the ASIC market. With ASIC designers considering programmable alternatives for many projects, design-flow compatibility is essential. According to the companies-which are, respectively, the leading suppliers of ASIC design tools and programmable logic devices-the tools offered under the new program provide a straightforward means for designers to evaluate the FPGA design flow within their familiar ASIC design environment.
Advanced synthesis will be provided through Synopsys' FPGA Express, while technology-specific optimization will be offered through its FPGA Compiler II, which includes a suite of features to make it compatible with the widely deployed Design Compiler ASIC tool. Additionally, robust place-and-route capability is provided through Xilinx's Alliance Series tools.
Xilinx, San Jose, is offering free 30-day evaluation copies of the software, which can be downloaded from www.xilinx.com/programs/alliance/synopsys/fc2.htm.
In conjunction with the tools, Xilinx and Synopsys, Mountain View, Calif., will co-host on March 8 a Web-based seminar on the design methodology, through E.N.E.N., the Education, News & Entertainment Network (www.netseminar.com). Separately, Xilinx, through its customer-training program, offers additional formal education in FPGA design for ASIC users.