Intel Corp.'s Plumas double-data-rate (DDR) chipset for two-way servers, disclosed this week for the first time at the Intel Developers Forum, will support another newly revealed processor code-named Gallatin in 2002.
Hermant Dhulla, Intel's director of enterprise chipset marketing, told EBN that Plumas will be the first in a family of chipsets for the volume two-way server market. Company executives Tuesday identified the upcoming Gallatin server processor as the first MPU to use the new chipset, when the MPU is introduced in two years to replace the IA-32-based Foster.
Dhulla said Plumas will consist of three chips: a northbridge, I/O bridge, and PCI/PCI-X bridge. In addition, the device will be among the first Intel chipsets to connect with the new InfiniBand bridge, which is interchangeable with PCI bridges. The Plumas also will feature memory error-correction code and chip-disable features.
According to Intel's roadmap, the Plumas chipset is scalable and can support a single processor server with 256 Mbytes of memory up to a range of dual processors with 16 GBytes of memory.
Dhulla said another new chipset, the 870, is slated to debut in late 2001 and will be a similarly scalable device for four-way and eight-way servers. The 870 will initially support the 64-bit McKinley server processor -- the successor to Itanium -- using DDR memory. As previously reported, the 870 can also support Direct Rambus DRAM with a different mix of components for high end workstations.
Dhulla said the 870 uses a new scalable-node controller that is flexible enough to adapt to any future changes in the processor front-side bus. The node controller connects with another chip, the scalability port switch, which Intel calls a "persistent interface." Dhulla said this means server OEMs won't have to change their designs to accommodate processor FSB changes because these are set to be handled in the node controller.
Two 870 chipsets, each supporting four processors, can be linked to form an eight-way server system.
Dhulla said the 870 has been designed as "a chipset architecture," not as a discrete product, so it can be scaled up in future generations. Instead of designing an entirely new chipset for each processor upgrade, the 870 architecture can allow future versions within the basic design, he said.
Dhulla said Intel's concept for future chipsets is to have a central library of macro-design modules that can used in a mix-and-match fashion to adapt future chipsets for optimized customer desires based on performance, cost, and power.
Intel provided only sketchy details on its most imminent new server chipset, the 460GX, which will support the first 64-bit Itanium processors. Itanium will be out in what Intel termed a "pilot launch" in the fourth quarter, ramping up to unspecified higher volume shipments in the first quarter of 2001.
The 460GX supports up to four Itanium processors linked to PC100 SDRAM memory. Intel declined to disclose either the front-side bus bandwidth or memory bandwidth, saying only that memory bandiwdth will be twice the Itanium FSB bandwidth.
The chipset has a separate system address controller for up to four PCI bridges and a separate I/O bridge.