Fujitsu Ltd. Thursday said it developed a structured ASIC that includes three standardized interconnect layers and embeds key IP macros in the base master.
Fujitsu said the structured ASIC will cut chip development time by 50% and reduce non-recurring engineering costs by about 30%.
Fujitsu is targeting the new ASIC at telecommunications equipment. The company claimed that in the last three years it was the largest Japanese ASIC vendor based on revenue.
Of six interconnect layers, three are standardized for basic circuitry, including eight sources of clock signals with phase-locked loops. Fujitsu said that leaves only three layers to be customized for customer specifications. A testing SCAN circuit and built-in self test (BIST) are also included.
Key IP macros are also embedded in the base master, which offers five built-in gates ranging from 455 kilogates to 3,416 kilogates, each with data I/Os running at 400Mbits/s. Fujitsu said it is also developing a base master capable of handling data at speeds up to 3.125Gbits/s.
The structured ASIC is made on a 0.11-micron process.