SAN JOSE -- Intel Corp. president Paul Otellini told the Intel Developer Forum Tuesday that within the next two to three years Intel will unveil a dual core 32-bit Xeon server processor, code named Tulsa.
Tulsa will follow the previously announced dual core 64-bit Itanium processor, code-named Montecito, which is to debut in 2005.
Otellini also confirmed that a multi-core Itanium, code-named Tanglewood, would follow Montecito, but declined to give a timetable for its release. He said Tanglewood will have 1 billion transistors, more than double the 410 million transistors on the current high-end Madison Itanium 2 chip. It also will be the first MPU core designed by the former Alpha processor design team in Hudson, Mass., that Intel acquired several years ago from Compaq Computer.
Otellini also disclosed a new hardware partitioning technology, Vanderpool, that will augment software by allowing processors to perform widely divergent operations at the same time, such as running two different operating systems or interactive programs simultaneously on different systems. He projected Vanderpool will be available within the next five years.
Otellini said Intel's previously-disclosed hardware security technology, La Grande, will be introduced in the next two to three years. La Grande will be implemented in both processors and chipsets in conjunction with new Microsoft Corp. security software. Among other safeguards, La Grande will protect main memory from unauthorized access by hackers, and prevent "Trojan Horse" plants by hackers that pick up a user's keystrokes.
To meet privacy concerns, hardware with La Grande technology will come in two versions -- one with the security features implemented and one with the feature turned off. Otellini said users can select either option.
Otellini appeared to counter industry reports that Intel's new Wi-Fi 802.11a/b wireless LAN chipset would be delayed, claiming the unit will ship this month. He said a tri-mode (802.11a/b/g) chipset would ship in the first half of 2004. Intel also plans to introduce new low power 802.11 chipsets, not only for the notebook market, but also for handheld devices.
Separately, Otellini said a new specialized media processor technology unveiled last week with the first chip slated for use by Xerox Corp. will over time be used inside microprocessor and chipsets.
Updating Intel's process technology roadmap, he said the company's first 65nm node chips will be produced in 2005. The 45nm node will come in 2007 and be the first to employ tri-gate transistors. He added that Intel has already made prototypes using a 32nm process slated for 2009 and a 22nm process technology planned for 2010.