PARIS Freescale Semiconductor Inc. and Synopsys, Inc. announced they have expanded their multi-year verification collaboration.
The progression to new process technology nodes every two years is easing, and the return on investments on Moore's Law is decreasing. The focus of the design industry is on hardware and software verification.
Freescale and Synopsys said their objective is to tackle verification complexity due to the integration of complex hardware.
A key focus will be placed on verification performance, efficiency and methodology but, above all, the two partners intend to manage "the ever-increasing cost of verification, which can encompass up to 75 percent of the total cost of product development."
In its quest for verification cost reduction, Freescale said it plans to address various verification metrics, including the efficiency of compute-farms and the productivity of engineers.
Synopsys claimed its verification team has added new features and capabilities to its traditional hardware verification tool set. It has integrated simulation with other key technologies such as testbench creation, assertion checking, coverage metrics, debugging. It has also worked on improving speed, where possible exploiting multicore compute infrastructures.
Contacted by EE Times, Synopsys said it was not able to divulge further details or comments.