Milpitas, CA - July 28, 2009 - Linear Technology Corporation has announced a family of 24 low-power 14-bit/12-bit, 125-Msps to 25-Msps, quad and dual ADCs that dissipate as little as one-third the power of competing ADCs. The flagship ADC is the LTC2175-14, a quad 14-bit, 125Msps ADC that dissipates only 558 mW (140 mW per channel).
The LTC2175 significantly reduces system power without sacrificing AC performance, offering signal to noise ratio (SNR) performance of 73.4 dB and spurious free dynamic range (SFDR) of 88 dB at baseband. Operating from 1.8 V analog and digital supplies, the ADC includes a sleep mode that reduces power dissipation to just 1 mW. Whether operating at full speed or in sleep mode, this ADC significantly lowers the power budget for highspeed multichannel designs such as multiple-input multiple-output (MIMO) WiMAX/LTE and 3G basestations, portable medical imaging and non-destructive testers.
Data is output from the LTC2175 in serial LVDS format to minimize the number of data lines. At 125 Msps, each channel outputs two bits at a time, using two lanes per ADC. At lower sample rates, a one bit per channel option is available. The device offers serial data communication and four ADCs in a small 7-mm x 8-mm QFN package, requiring less board area for data I/O lines and simplified layout.
The LTC2175 includes an SPI-compatible interface that allows users to choose between a variety of data settings that reduce digital feedback and simplify design. Options include a data output randomizer that reduces digital feedback, seven programmable LVDS output current levels, internal 100-Ohm LVDS output termination resistors, and digital output test patterns. These settings can be programmed via SPI or hard-wired for a reduced set of operating modes.
The LTC2175 is part of a family of pin-compatible quad ADCs, offering 14-bit and 12-bit resolution from 25 Msps up to 125 Msps. All devices are supported with demonstration boards and free software.
For further information visit www.linear.com.