Analog designers, digital IC designers/verification engineers, place and route engineers and project managers in Cambridge and Bristol in the UK are invited to attend a free technical seminar presented by Cadence - part of a series of Technology on Tour days throughout Europe that has been organised by Cadence throughout October and November 2008. The Bristol event will take place on 11th November, and the Cambridge event on Tuesday 18th November.
The seminar will address the latest technology and integrated design flows to consider when designing high-performance chips and systems, with a special focus on mixed-signal design, from verification to implementation.
Among the topics under discussion will be the need for a 'mixed-signal on top' methodology when designing ics with a lot of analog and digital content; what the best approach is for modelling mixed signal blocks - Spice, VerilogAMS VHDL-AMS or wreals?; and interoperability between Cadence's Encounter and Virtuoso platforms for mixed signal chip floorplanning, placement and routing.
To register or find out more, visit Cadence's events page