LONDON – Fabless chip company Icera Inc. has announced it is sampling the latest chip set and software in its Espresso series of platforms targeted at HSPA+ smartphones.
The Espresso 450 comprises Icera's latest baseband and RF ICs and delivers quad band HSPA+ up to 28-Mbps together with full quad band 2G/3G voice support functions in a packaged footprint of 700 square millimeters. Espresso 450 includes a radio interface layer for the Android operating system.
"Icera has evolved quickly from its start-up phase to being established now as one of only two major vendors in the data-intensive mobile broadband chipset market, with Icera being famous for continuously offering the world's highest performing chipsets," said Stan Boland, president and CEO of Icera (Bristol, England), in a statement.
Espresso 450 uses the ICE9225 multi-mode transceiver chip and the Livanto ICE8065 soft baseband processor. The ICE9225 radio is implemented in low power 65-nm CMOS technology. The ICE8065 is implemented in 40-nm CMOS and is the soft baseband that runs all of the modem physical layer, protocol stack, voice codecs, echo cancellation, noise reduction and equalization in software.
Icera is engaged with leading application processor partners on pre-integration of the Espresso 450 platform with the latest application processor platforms to accelerate the fast design of complete smartphones. Samples of first phones using Espresso 450 are expected to ship late in 2011.
Espresso 450 is an RF module that can be used in cell phones for implementing RF Section of the Cell Phone, this will be finding a very good applications in the small scale manufactures as it has got interface for Android.
The article is still wrong unfortunately. 700mm2 is the PCB footprint, not the packaging footprint! The platform includes a a 7x7 baseband, a 6x6 radio, and a PMIC with a very small wafer level package. That means the total packaging footprint is less than 100mm˛. That's a 3-chip solution whereas Infineon/ST-Ericsson have 2-chip solutions, but at least in Infineon's case that's just stacking the PMIC on the baseband which I fail to see how it would provide a cost benefit versus a WLP PMIC.
The remaining 600mm2 of PCB footprint is taken by power amplifiers, memory, and passive components. I honestly don't know why Icera even bothered providing that number because it's both slightly confusing (as Peter's misunderstanding highlights) and rarely comparable to anything else because you can optimise more for area at the detriment of cost or other metrics.
The Option GTM501 module with Icera's 65nm baseband and 130nm RF chip took only 750mm2, so with Espresso 450 and a similar level of area optimisation and DRAM stacking I wouldn't be surprised if 400mm2 was possible in theory.
Anyway the big news here is that Icera finally has a voice certified platform and they have reference platforms with multiple application processor vendors. The phrasing of the press release is rather vague, but I assume they're going to show ODM phones at MWC (that carriers will pick up and self-brand) and try to win more major phone OEMs. Let's wait and see how that goes...
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.