SAN CLARA, Calif. -- At DesignCon here Apache Design Solutions released CPM v2.0, its next generation Chip Power Model (CPM) intended for co-analysis/co-optimization of the chip, package, and system.
Resonance-aware models in version 2.0 let designers determine the optimal placement and configuration of the package and PCB decoupling capacitance to help manage power and noise.
Apache claims CPM v2.0 is ideal for wireless and automotive markets where 3-D and System-in-Package designs are used.
In 3D-IC and SiP designs, thermal integrity becomes a major challenge for chip-package-system co-design. The power mapping in CPM v2.0 enables package designers to accurately predict the thermal distribution and hot spots of multiple die in a stacked die packaging.
Also, CPM v2.0 delivers a power model that contains the LDO circuitry that is critical to system-level EMI and EMC validation.
"Apache pioneered the market with its first delivery of CPM, and as adoption and application of the model continues to grow, our close partnership with customers has driven us to provide more advanced features to meet their needs," said Andrew Yang, CEO of Apache Design Solutions, in a statement.
Apache’s resonance-aware CPM v2.0 model considers the LC resonance frequency of the system and automatically generates an on-die switching scenario operating at or near the system resonance. This enables system designers to access a CPM representing the worst case switching scenario that can be used for stress testing the CPS design.
CPM v2.0 models on-die power transient waveform over a long duration to capture the envelope modulating the high frequency switching. This represents middle to low frequency components on the chips which impacts the global PDN (power delivery network) and needs to be handled by package and printed circuit board power supply system. The power transition model allows system designers to simulate load step conditions to identify and debug weaknesses in their package and system designs.
The first generation compact model represented full-chip PDN with distributed on-die power and ground resistance, decoupling capacitance, and inductance of the digital core, memories, and IP. The release of CPM v2.0 adds considerable advancements to help meet the increasing accuracy and usability requirements of system designers, according to Apache.
For example, CPM v2.0 offers enhanced usability with user configurable models for system-level ‘what-if’ analysis of various IC switching scenarios. Chip designers can create multiple current profiles for various blocks within the design, enabling system designers to simulate power switching scenarios and exhaustively verify their system.
Apache will hold its second chip-package-system (CPS) workshop at DesignCon this Thursday, Feb.3. It will expand on last year’s session. That session brought together experts in the area of CPS convergence and focused on EMI/EMC for various industries. This year's workshop will focus again on EMI/EMC applications and provide case studies and real design examples from the following: Daryl Beetner (Missouri University of Science and Technology), Cornelia Golovanov (LSI Corp.), and Thomas Steinecke (Infineon Technologies).
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.