LONDON – Anobit Technologies Ltd. has said it has begun high volume production of its MSP2020 NAND flash memory controller in cooperation with Hynix Semiconductor Inc. It has also brought forward a supporter that says its IC can help address NAND flash memory that has been reduced to 3,000 read/write cycles in leading-edge devices.
Anobit was founded in 2006 to make solid-state drives. It's MSP (Memory Signal Processing) technology is a combination of error correction and memory management schemes that compensates for errors and evens out wear thereby allowing higher apparent performance.
The MSP2020 supports up to two ONFI-compliant NAND interfaces to a host processor, and can support product configurations from 4- to 128-Gbytes. As such the MSP2020 is suitable for high-performance mobile computing devices. It enables the use of commercial-grade two-bits-per-cell and three-bits-per-cell NAND flash within endurance- and performance-intensive embedded computing applications.
"In the span of just five years, the endurance of mainstream NAND flash has plummeted from 100,000 program/erase cycles to approximately 3,000 cycles, and the industry push toward three-bit-per-cell MLC NAND will place further downward pressure on NAND endurance. In parallel, mobile computing devices will continue to fuel demand for higher NAND endurance and performance," said Gregory Wong, founder and principal analyst, Forward Insights, in a statement issued by Anobit (Herzeliya, Israel). "Anobit's innovative MSP technology is well positioned to close the NAND endurance gap, and in so doing, help fuel the proliferation of NAND flash memory into a variety of consumer electronics and computing markets."
"The MSP2020 flash controller has been qualified for production with Hynix 2xnm MLC NAND by one of our key customers," said J.S. Yang, Hynix vice president of engineering, in the same statement.
Poor endurance is just one aspect of newer NAND devices that is problemmatic. The other is increasing latency because of the much slower multi-level cells and the the increasing time neeeded for error correction before any of the retrieved data can be used. Cell latency used to be of the order of 20-30uS and 1-bit error correction added almost nothing to that. Now cell latency is 80uS or more and typical NAND controllers add far more.
Our application, which demands low random access latency, used to be practical with NAND but with present trends, may become impractical before we can deliver a product. Does the MSP controller help the latency issue?
You are correct about wear leveling and error correction codes. This product has something else, which we call Memory Signal Processing. It is about applying signal processing methods to the analog voltage levels inside the memory array.
Wear leveling and FEC are nothing new in SD cards, thumb drives and SSDs. Otherwise, the FAT table (written every time you write to a file) wouldn't last long. A flash manager needs to remember sectors that go bad, provide wear leveling, and do forward error correction among other things. A press release wouldn't necessarily say "Ours is better than Theirs because...".
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