LONDON – EDA company Atrenta Inc., working with the IMEC research institute on a 3-D integration project, has developed a planning and partitioning design flow for heterogeneous 3-D stacked IC assemblies. Atrenta (San Jose, Calif.) and IMEC (Leuven, Belgium) have said they plan to demonstrate this design flow on the Atrenta booth at the Design Automation Conference, which takes place June 6 to 8 in San Diego, California.
The design flow combines floor plans produced by Atrenta's Spyglass physical 3-D prototyping tools with IMEC-developed thermal and mechanical stress models. Target applications include: products for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.
In 3-D design the number of potential partitions and interconnection solutions is large, including options on silicon interposers and orientation of die. Other challenges include thermal performance and mechanical stress caused by assembly and final configurations.
Exploring different solutions through full designs is not considered viable due to time and expense. Therefore getting feedback from virtual partitioning and prototyping before implementation is potentially beneficial.
Key parts of the Atrenta 3-D design flow are compact thermal and mechanical models developed by IMEC and validated using DRAM-on-logic packaged components.
The DAC demonstration will include design partitioning across a 3-D stack with routing congestion analysis, through silicon via (TSV) placement and backside redistribution layer routing support as well as display of thermal profiles on the 3D floor plan, IMEC said.
Some EDA startups (who shall remain nameless!) went bust chasing the 3D pathfinding mirage. 3D stacked chip design using TSV's is a system-level challenge. By "system" I mean a complex system of interaction between electrical, mechanical, electromechanical, thermal and thermo-mechanical systems that need to be addressed in the design stage. Overlooking this at the design stage will only lead to costly & time-consuming iterations with prototyping.
Of the big three EDA, I believe Mentor is in the best position to address 3D design challenges with the suite of tools it currently has. It will need some missing pieces (like mechanical simulation) to complete the picture. It might as well pick up the assets of some defunct 3D pathfinding companies in the process!
Note that Atrenta is not the only one to offer 3D pathfinding, there is R3Logic...
Dr. MP Divakar
I am really curious why the big guys SNPS/CDNS/MENT didnt acquire Atrenta yet, which is the normal practice in EDA industry! But Atrenta on their part seems not waiting for an acquisition and is making good progress and moving into new domains like 3D design from their traditional RTL analysis tools. Good luck guys.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.