LONDON – EDA company Atrenta Inc., working with the IMEC research institute on a 3-D integration project, has developed a planning and partitioning design flow for heterogeneous 3-D stacked IC assemblies. Atrenta (San Jose, Calif.) and IMEC (Leuven, Belgium) have said they plan to demonstrate this design flow on the Atrenta booth at the Design Automation Conference, which takes place June 6 to 8 in San Diego, California.
The design flow combines floor plans produced by Atrenta's Spyglass physical 3-D prototyping tools with IMEC-developed thermal and mechanical stress models. Target applications include: products for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.
In 3-D design the number of potential partitions and interconnection solutions is large, including options on silicon interposers and orientation of die. Other challenges include thermal performance and mechanical stress caused by assembly and final configurations.
Exploring different solutions through full designs is not considered viable due to time and expense. Therefore getting feedback from virtual partitioning and prototyping before implementation is potentially beneficial.
Key parts of the Atrenta 3-D design flow are compact thermal and mechanical models developed by IMEC and validated using DRAM-on-logic packaged components.
The DAC demonstration will include design partitioning across a 3-D stack with routing congestion analysis, through silicon via (TSV) placement and backside redistribution layer routing support as well as display of thermal profiles on the 3D floor plan, IMEC said.
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