LONDON – Fabless many-core processor vendor Tilera Corp. has launched its Tile-Gx 3000 family of 40-nm processors claiming they provide a 10-fold improvement over Intel's SandyBridge processor in terms of performance-per-watt.
The 64-bit processors are designed for cloud computing datacenters and come with 36, 64 or 100 cores that operate at clock frequencies up to 1.5-GHz. The 36-core version consumes 20 watts and samples in July, Tilera (San Jose, Calif.) said. The two larger versions consume 35- and 48-W, respectively, and are due to sample early in 2012. The three chips have total amounts of on-chip memory of 12, 20 and 32-Mbytes in ascending complexity order, the company said.
The company did not say how much the chips will cost.
One reason that Tilera can perform so well, the company asserted, is that the processors have been optimized for datacenter applications such as database mining and video transcoding.
In the 3000 series each core features a three-issue, 64-bit ALU with its own virtual memory system. Each core includes 32-kbytes of level-one instruction cache, 32-kbytes of L1 data cache and 256-kbytes of L2 cache, with up to 32-Mbytes of L3 coherent cache across the device. Processor utilization is optimized using memory stripping that uses up to four 72-bit DDR3 memory controllers supporting up to one terabyte (TB) total capacity. The 3000 series integrates networking hardware for preprocessing, load balancing, and buffer management of incoming traffic.
The 3000 series chips are designed to handle most common cloud applications and runs Linux release 2.6.36.
"We have been working with the largest cloud computing companies for two years to design a processor that addresses their biggest pain points," said Ihab Bishara, director of server solutions at Tilera, in a statement. "The Tile-Gx 3000 series has features like 64-bit processing, virtualization support and high processor frequency, which were specifically implemented for our web customers. The era of 20 to 30 percent incremental gains is over. The Gx-3000 series provides the order of magnitude improvements the industry is looking for."
Graphical depiction of Tilera's tile architecture, which the company says is power efficient and highly scalable. Source: Tilera Corp.
3D scaling could be important if there is high interdependence between the operations of each CPU, but I maintain that we may have to build new computing models to really take advantage of systems built around CPUs like this. Separate memory for each processor is a good start, since it relieves the bottleneck of access to shared memory. Data centers are a good application for this, because they often work on large numbers of independent transactions. By the way, we may also have to look at the nomenclature. I just realized that this isn't really a Central Processing Unit (CPU). It's more like a Central Processing Pool (CPP?). For that matter, is the 'processor' the chip or each of the sections of it? The same word is used for both in this article.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.