LONDON – Intel Corp. and Micron Technology Inc. have announced the development of a 128-Gbit NAND flash memory made using an improved 20-nm manufacturing process technology for flash that includes high-K metal gate (HKMG) transistors.
The companies claimed it is the world's first monolithic 128-Gbit memory and said they are going into mass production of a 64-Gbit 20-nm NAND flash part in the same process immediately and expect to ramp production of the 128-Gbit device in the first half of 2012.
Intel and Micron did not describe the process as being 20-nm class, something that other manufacturers have done to refer to process that is somewhere between 20- and 29-nm. It has previously been reported that Intel and Micron had a 64-Gbit NAND flash was implemented in a 25-nm process.
The latest parts were developed at Intel and Micron's joint venture, IM Flash Technologies (IMFT). The 128-Gbit memory uses multilevel sensing in each cell, although the companies did not indicate how many bits per cell. The companies also said the part is the first to use a planar cell structure that overcomes scaling constraints on standard floating-gate NAND flash memories by integrating the HKMG gate stack on NAND production. HKMG gate-stack transistors have been in used by Intel for logic processes for several nodes, but this is believed to tbe the first application to a memory component.
Intel and Micron said they are ramping production of the 20-nm 64-Gbit NAND flash memory in December and would expect a rapid transition to the 128-Gbit device in 2012. Samples of the 128-Gbit device will be available in January, followed by mass production in 1H12.
The 128-Gbit memory meets the supports 333 megatransfers per second supporting applications in smartphones, tablet computers and solid-state drives. For modules eight 128-Gbit die will provide a terabit of storage.
"It is gratifying to see the continued NAND leadership from the Intel-Micron joint development with yet more firsts as our manufacturing teams deliver these high-density, low-cost, compute-quality 20-nm NAND devices," said Rob Crooke, Intel vice president and general manager of Intel's non-volatile memory solutions division.
I have no idea. But I will ask Intel and Micron on your behalf.
Be prepared. They may say that this is all they wish to say on the topic except to people who are prepared to sign a non-disclosure agreement.
This is from Dan Snyder a PR manager at Intel:
"The smaller cell size enabled by the 20nm litho using the planar cell structure and hi-k metal gate (HKMG) allowed us to double the monolithic die capacity of the previous 25nm generation, where 64Gb was the maximum capacity that could fit in standard memory packaging. The higher dielectric constant of the hi-k enabled the required coupling between the floating gate and the control gate on the 20nm based cell, so the use of HKMG was critical for the production of any capacity NAND on 20nm (both our 64Gb and 128Gb), so therefore HKMG played a critical role in enabling the increase in monolithic die capacity to 128Gb.
To paraphrase -- Intel-Micron needed to use HKMG in the gate-stack to get the 20-nm process to work. So without HKMG they couldn't have done the shrink from 25-nm and got the doubled memory cell density.
Just yesterday I heard a news story here in San Diego about Gordon, the new supercomputer at the local SD Supercomputer Center. It has a 9X speed increase over last year's speed champ due to the use of what were described as 'massive' SSD's for storage. It looks like it will soon be due for an upgrade...
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