LONDON – German chipmaker Infineon Technologies AG has launched its XMC4000 family of 32-bit microcontrollers based on the Cortex-M4 core licensed from ARM Holdings plc.
The XMC4000 family is intended to support three trends in industrial applications, Infineon said, namely: increased energy efficiency, broad support for communications standards and reduced software complexity during development. The company is offering development support for a graphical interface for software authorship and automatic code generation.
XMC stands for "Cross-Market Microcontroller" and Infineon is positioning the family between its 16-bit XE166 family and its 32-bit TriCore family.
The XMC4000 portfolio consists of five series: XMC4100, XMC4200, XMC4400, XMC4500 and XMC4700 that are differentiated from each other in terms of core frequency, memory capacity and peripheral functions and number of I/Os. The portfolio supports DSP functionality, floating-point and on-chip flash memory.
The integrated development environment known as "DAVE 3" is Eclipse-based and provides a free GNU compiler, debugger and data display utilities which can be extended with third-party tools. DAVE 3 also supports automatic code generation based on predefined software components, the so-called DAVE Apps.
The DAVE Apps are configured using a graphical user interface. The code that is generated can be directly compiled, debugged and displayed in DAVE 3 – or imported into third party tools for further processing. Infineon said it has cooperated with more than 20 partners who can support the XMC4000 family in various ways.
Google helped find a more complete chip-analysis here (needs translate)
and a road map here - just Google :
Hints that 1e@10k claim could be ?
For a part that samples soon, this has very little real information.
I did find this : ["The XMC4000 series has a cpu subsystem, dsp functionality, a floating point unit, a fast flash memory with 22ns read time and error correction code, large sram and extended peripheral functions. These include new timer modules; up to four parallel 12bit a/d converters with a sampling rate of 70ns and a conversion time of 500ns; up to two 12bit d/a converters, up to four high resolution PWM channels (150ps); and integrated delta-sigma demodulator modules and touch button modules. "]
and in their FAQ they claim this is NOT Automotive applications. (yet have multiple CAN bus?)
No prices, apart from a cryptic 1e to 7e indicator.
I wonder what 1e gets you ?
Lots of m4 options are available now. The difference is really going to come down to power mode and/or peripheral function differentiation. Additionally, the support for higher level functions to easy peripheral programming and firmware IP for functions like motor control will make a big difference. Lets see more about these topics in similar product announcements going forward.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.