"Our XMC4000 family combines optimized peripherals with the advantages of the widespread ARM architecture for industrial applications," said Stephan Zizala, senior director responsible for industrial and multimarket microcontrollers at Infineon, in a statement. "Our customers in industrial electronics benefit from our many years of application experience that result in convincing novelties: flexible timers, fast ADC's, fast and robust flash memory and extended temperature ranges of up to 125 degrees C. Using the development environment DAVE makes familiarization with the XMC4000 family convenient, time-saving and free of charge."
The first series to be launched is the XMC4500. These offer a 120-MHz CPU and up to 1-Mbyte of embedded flash, 160-kbytes of RAM and a range of peripheral and interface functions.The package options are LQFP-144, LQFP-100 and LFBGA-100.
The portfolio will range in performance from 80-MHz clock and 64-kbytes of flash at the XMC4100 low end to 180-MHz and 2.5-Mbytes of flash at the XMC4700 top end, which is currently in definition.
Samples of the XMC4500 series and DAVE 3 will be available from March 2012, Infineon said. High-volume production of the XMC4500 products is due to start in May 2012.
For development support Infineon offers a modular design kit with which up to three additional application boards can be connected to the basic design board, depending on the respective application requirements. Samples of the XMC4400, XMC4200 and XMC4100 series will be available from the fourth quarter of 2012. Depending on the XMC4000 series and package selected, the unit price for a XMC4000 microcontroller ranges between 1 euro and 7 euro (about $9), Infineon said.
Google helped find a more complete chip-analysis here (needs translate)
and a road map here - just Google :
Hints that 1e@10k claim could be ?
For a part that samples soon, this has very little real information.
I did find this : ["The XMC4000 series has a cpu subsystem, dsp functionality, a floating point unit, a fast flash memory with 22ns read time and error correction code, large sram and extended peripheral functions. These include new timer modules; up to four parallel 12bit a/d converters with a sampling rate of 70ns and a conversion time of 500ns; up to two 12bit d/a converters, up to four high resolution PWM channels (150ps); and integrated delta-sigma demodulator modules and touch button modules. "]
and in their FAQ they claim this is NOT Automotive applications. (yet have multiple CAN bus?)
No prices, apart from a cryptic 1e to 7e indicator.
I wonder what 1e gets you ?
Lots of m4 options are available now. The difference is really going to come down to power mode and/or peripheral function differentiation. Additionally, the support for higher level functions to easy peripheral programming and firmware IP for functions like motor control will make a big difference. Lets see more about these topics in similar product announcements going forward.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.