LONDON – Tensilica Corp. (Santa Clara, Calif.) has produced another core in its ConnX series, the BBE32UE, which is optimized for software programmable LTE-Advanced user equipment.
The BBE32UE coupled with Tensilica's dataplane processors (DPUs) enable LTE-Advanced PHY layers to be built in 28-nm CMOS that consume less than 200-mW excluding turbo coding, the company said.
Tensilica said it has already achieved success in the LTE market and is now pushing towards LTE-Advanced and has lead customers working on the BBE32UE IP core for baseband SoC designs.
The core has been optimized for catergory 6 (300-Mbit/s downlink, 50-Mbit/s uplink) and category 7 (300-Mbit/s downlink, 150-Mbit/s uplink) LTE. Using the ConnX BBE32UE DSP core, coupled with Tensilica Baseband Dataplane processors (DPUs), a fully software programmable, flexible modem for LTE-Advanced user equipment can be realized in less than 200 mW (28 HPL process). It can also support 2G, 3G, LTE and HSPA+ standards.
The transition from LTE to LTE-Advanced can require up to a 5x algorithm and data rate computation increase, Tensilica said. Without significant changes many DSP approaches will simply not be able to achieve LTE within acceptable power budgets, said Eric Dewannain, Tensilica's vice president and general manager, baseband business unit.
Tensilica has worked with leading handset partners and MimoOn GmbH (Duisberg, Germany), a developer of LTE software and software-defined radio technology, to optimize the architecture and the instruction set of the ConnX BBE32UE for algorithms required by user equipment applications and stripped out what is not needed.
It would be interesting to see a comparison between this approach and the FPGA approach. What are the advantages and disadvantages of each? What isn't possible to do with an FPGA approach that the Tensilica solution can?
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