LONDON – JTAG Technologies BV (Eindhoven, The Netherlands), a vendor of test and debug tools based on boundary-scan, is launching CoreCommander at the DESIGN West conference and exhibition due to be held in San Jose, Calif., March 26 to 29.
By using JTAGLive and CoreCommander, engineers can activate the on-chip debug modes of a range of popular cores to affect kernel-centric testing, the company said. CoreCommander support includes ARM, Cortex, XScale, PowerPC and TriCore architectures.
CoreCommander routines are suitable for diagnosing faults on "dead-kernel" boards in either design debug or repair, since no on-board code is required to set memory reads and writes, the company said.
CoreCommander is Python-based and complements the established JTAGLive Script product, allowing access to mixed-signal parts such as ADCs and DACs and also synchronised testing to full boundary-scan devices.
JTAG Technologies is also using DESIGN West to launch Autobuzz, a tool that learns a connectivity signature of all boundary-scan parts within a design from only the BSDL models of those parts. Autobuzz expands the "seek and discover" mode of BuzzPlus and automatically gathers circuit data of a known good board and then performs a full connectivity compare against the faulty circuit. Autobuzz is a useful tool for repair and rework technicians, especially when design data is missing or incomplete.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.