LONDON – Fabless FPGA vendor Achronix Semiconductor Corp. (Santa Clara, Calif.) has announced details of its Speedster22i HD and HP product families, claimed to be the first FPGAs to be built on a 22-nm manufacturing process technology.
The devices are the result of a foundry agreement with Intel Corp. announced in November 2010 and the first devices are due to sample in the third quarter of 2012.
Both the HD (high density) and HP (high performance) families come loaded with a variety of high-speed data communications interfaces hardwired. These include 10/40/100G Ethernet MACs, 100Gbit Interlaken channels, PCI Express and DDR3 memory channels that run at up to 2133 Mbps. In the case of the HD1000 device these are two, two, two and six respectively.
This optimizes the Speedster22i FPGAs for work in networking and telecommunications equipment although the company stresses that the devices can find applications in servers, high-performance computing, military, industrial and scientific applications. The large number of high speed memory channels provides the industry's highest bandwidth FPGAs, Achronix claimed.
Achronix' existing product range is based on 65-nm process technology and the move to Intel's 22-nm FinFET process allows Speedster22i family to consume half the power at half the cost of high-end, 28-nm FPGAs.
"We worked closely with leading companies in the communications market segment to design our FPGAs to meet their performance, power, and cost requirements," said Robert Blake, Achronix's president and CEO, in a statement. "The combination of Intel's 22-nm process leadership and our innovation in both the core fabric and embedded hard IP for targeted applications means that our customers will have a high end FPGA solution that is half the power and half the cost of competing FPGAs," he added.
Achronix is starting its Speedster22i family with HD1000 device which includes logic equivalent to about 1 million 4-input look up table blocks, the fundamental blocks in many FPGA architectures. In fact there are only 700,000 user-programmable LUTs as Achronix values its hard-wired IP as being equivalent to about 300,000 LUTs. The HD1000 also includes 84-Mbits of embedded RAM. Eventually there will be four members of the synchronous HD range (see table) that will capable of being run at a maximum clock frequency of about 600 or 700-MHz, according to John Lofton Holt, chairman and founder of Achronix.
The HP family is due to start sampling in the first quarter of 2013, Holt said.
The HP FPGAs use a self-timed architecture to allow operation at up to 1.5 GHz clock frequency and are 3 to 4 faster than synchronous FPGAs, the company said. The largest member of the HP family, the HP560, has 250,000 programmable LUTs and 64-Mbits of embedded RAM.
Click on image to enlarge.
Table: Six FPGAs cover performance and density in Speedster22i range. Source: Achronix
The use of the Intel 22-nm FinFET process technology brings an advantage in terms of half the leakage power of 28-nm equivalents and 20 percent less power consumption of custom logic implemented in the FPGA fabric. The result is up to 50 percent less total power consumption that 28-nm FPGAs, Achronix claimed.
Achronix did not give any indication of what it will charge for HD or HP FPGAs. Engineering samples of the HD1000 will begin shipping in Q3 2012. The remaining HD and HP devices will be rolled out in the following 12 months.Related links and articles:
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