PORTLAND, Ore.—Broadcom Corp. Tuesday (April 24) announced its fourth-generation Ethernet network processor, which it claims is the industry's first chip to use massive parallelism by virtue of its 64 packet-processing cores running at one gigahertz. Providing full-duplex 100Gbit per second performance, it can also be configured to provide a dozen 10-Gbit channels.
"By 2015, there will be twice as many devices connected to the Internet as there are people in the world, many of which will be streaming video," said Dan Harding, senior director of marketing, infrastructure and networking at Broadcom. "As a result of this increasing demand for bandwidth, the core of the network is going to need upgrading to 100Gbit Ethernet over the next four years."
Broadcom claims that by the end of 2012, the number of Internet-connected devices will exceed 7 billion. Over the next four years the majority of the content accessed from mobile devices will be high-bandwidth streaming video, according to Broadcom. What's worse, application downloads will balloon to 47 billion per year, according to the firm.
To meet this demand, Internet service providers are quickly adopting 100-gigabit-per-second Ethernet, which is estimated to grow at a rate of 170 percent over the next five years, according to Infonetics Research Inc. (Campbell, Calif.)
Server Ethernet ports running at 100 gigabits per second will grow at a rate of 170 percent over the next four years.
Broadcom claims that it has addressed the need for more bandwidth with higher levels of integration which enabled it to reduce the power and area of its fourth-generation network processor by 80 percent. And with its multi-threading support and specialized accelerators, its new network processor technology can offload many tasks that previously required external field-programmable gate arrays (FPGAs).
"The key technology that differentiates our 100 gigabit network processor are our seven cores dedicated to necessary tasks such as algorithmic look-up and packet generation," said Nicolas Tausanovitch, senior product line manager of infrastructure and networking. "By taking on tasks that previously had to be performed external FPGAs and expensive SRAM, designers using our chip can cut now the complexity and bill-of-materials cost for their line cards."
Using 40-nanometer design rules for its array of 64 packet processors, the BCM88030 also includes seven on-chip accelerators for common functions including a programmable algorithmic look-up engine for massive IPv6 tables using low cost DDR-3 DRAM, algorithmic access control list using Broadcom's proprietary knowledge based processor, as well as a high-speed packet parser and classifier.