MUNICH, Germany – Cadence Design Systems Inc. (San Jose, Calif.) announced a couple of extensions in its offering of intellectual property at the Cadence Live European user conference on May 15.
The company announced in-circuit acceleration of designs being simulated and emulated using Cadence's Incisive and Palladium products. The company also announced extensions to the verification IP catalog covering a number of well known interconnect standards including AMBA AXI versions 3 and 4 and ACE, PCIe versions 2.0 and 3.0, USB 3.0, 10-Gbit/s Ethernet, SATA 3, and HDMI 1.4.
The in-circuit acceleration results in up-to-10-times increased efficiency during system-level validation and root cause analysis, Cadence claimed. This is presumably when compared against the use of Cadence tools without in-circuit acceleration. The description up to 10x includes all the possibilities below that including 1x and 0.5x.
“We have reduced the time to closure on difficult, long running workloads, which enables us to increase our hardware and software coverage while reducing the overall test plan execution time,” said Alex Starr, emulation architect at Advanced Micro Devices Inc. on his company’s use of in-circuit acceleration.
More information about in-circuit acceleration can be found in Brian Bailey's write up of the Cadence offering here.
Cadence also used the opportunity of Cadence live in Europe to launch an IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the solid-state drive (SSD) market. Brain Bailey also covers this on EDA Design Line here.
Can someone tell me whom Cadence is competing with? Is it Synopsis or Tanner. I think this company is trying so hard to dominant but I cannot see it in the market valuation. So why is this industry leader not getting the bucks?
The process changes here are for the developments to be incorporated in the design environment. The claimed speed is just the way of one type of offer to the Cadence customer, what actually the user will get, depends on how is the process of the design and how better the design can make used of it.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.