LONDON – Altis Semiconductor SA, the specialty foundry bought by French entrepreneur Yazid Sabeg from IBM and Infineon in 2010, has announced the release of updated process design kits for 130-nm specialty technologies.
The baseline CMOS 130-nm process, which includes support for copper metal, came with Altis (Corbeil-Essonnes, France) when it was sold by its previous joint-venture parents IBM and Infineon. The latest PDKs include mixed-mode low-power CMOS (ATS-130-LP), RF-CMOS (ATS-130-RF) and embedded-Flash (ATS-130-FL). Updated EDA tools support has been included in the PDKs.
The PDKs are based on Cadence Virtuoso v6.1 and the OpenAccess database, Altis said. The latest PDKs extend the capabilities of previous versions with enhanced functionality and expanded EDA support. Altis provides the migration scripts to ease the transfer of existing legacy designs to the new PDK structure.
The PDKs contain so-called SKILL parameterized cell generators and supports design-rule-driven editing and the Virtuoso space-based router for chip, block and device-level routing. The PDKs support Momentum from Agilent which is a product for 3-D planar electromagnetic simulations of RF passive components and Agilent's GoldenGate RFIC simulator.
The Altis PDK's address the demands of complex RFIC and automotive designs with automotive-qualified digital standard cell libraries and 3.3- and 5-V I/O pad libraries.
I'm not sure if you understand the cubic dollars required to play in 28nm. The figures I have seen for MPW/Shuttle space on 28nm are about $100k/mm^2. And I don't think it makes any sense to tape out a 2mm^2 chip in 28nm... it'd be entirely padcage. So to put your design on an MPW you're looking at nearly 7 figures. And if your chip is heavily analog, you might not save much area vs. 130nm anyhow.
And from the other end, setting up a 28nm fab will cost a couple billion dollars, and there is no guarantee you'll even get a customer. At least if these guys don't get a customer, they aren't billions of dollars in the hole ;-)