SAN FRANCISCO—EDA vendor Mentor Graphics Corp. said Wednesday (May 30) that foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) would use Mentor's Calibre SmartFill dummy fill solution in its 20-nm manufacturing process.
According to Mentor (Wilsonville, Ore.), SmartFill analysts and automatic filling capabilities in its Calibre YieldEnhancer product address new 20-nm fill requirements that cannot be achieved with traditional dummy fill approaches. Calibre SmartFill delivers smaller post-fill GDS database size and faster runtimes, allowing designers to meet IC fill constraints in a single pass without manual customization or modification, and with minimal impact on circuit performance, according to Mentor.
“Adding fill to advanced IC layouts is about much more than just controlling planarity in manufacturing,” said Jean-Marie Brunet, director of product marketing for Calibre DFM and place-and-route integration at Mentor, in a statement. "Calibre SmartFill gives designers a fast and automated solution that creates the precise amount, shape and location of fill, not only to ensure that layouts meet complex manufacturing requirements, but also to maintain design intent."
According to Mentor, the move to more advanced nodes has pushed fill requirements beyond traditional fill approaches. In addition to improving planarity, fill now needs to handle CMP-ECD, etch, lithography, stress and rapid thermal annealing (RTA), Mentor said. A more advanced solution must deal with those effects concurrently and still provide ease of use and design flow integration, the company said.
The SmartFill capability in Mentor's Calibre YieldEnhancer provides advanced capabilities such as multi-layer fill shapes and user-defined fill cells that are automatically inserted into a layout based on analysis of the design, Mentor said. It also supports continuous, multi-dimensional functions in place of linear pass-fail conditions, enabling finer resolution of complex fill algorithms that cannot be performed with single-dimensional design rules alone, according to the company.
"At 20-nm an effective fill strategy is important for successful manufacturing," said Suk Lee, senior director of TSMC's Design Infrastructure Marketing division. "Calibre’s integrated fill analysis and cell-based approach makes fill more precise and makes writing fill decks easier, while achieving target runtime and output file size."
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